how to make reset signal "1" and later "0" in between the design

hello everyone,

i have written a verilog code where initially clk=1'b1; rst=1'b1; #2 rst=1'b0;
rst signal is zero throughout the design but at the third instantiated module i again want the rst to be "1" and later again "0".how can i make it ?

verilog code:

module nik(x_1,y_1,clk,rst,result);
parameter size1=8;
input[size1:0]x_1;
input[size1:0]y_1;
input clk,rst;
wire[size1:0] exp_outx; /* synthesis keep */
wire[size1:0]exp_outy;//RSU OUTPUT
wire[size1:0]sub1;//
wire [size1:0]sub2;
wire en1;
wire en2;
output[size1:0]result;
radixsu #(size1)r1(x_1,clk,rst,exp_outx,sub1,en1);//rsu for input x
radixsu #(size1)r2(y_1,clk,rst,exp_outy,sub2,en2);//rsu for input y
rest #(size1)r3(x_1,exp_outx,exp_outy,sub1,sub2,clk,rst,result);//here i want the rst signal to be "1" so that i can initialize values in rest module and later proceed with functionality...

endmodule


kindly help me guys...
thank you

Re: how to make reset signal "1" and later "0" in between the design

Synthesis or simulation? You didn't mention.


Probably simulation since you say "clk=1'b1; rst=1'b1; #2 rst=1'b0;"


Well, make it "clk=1'b1; rst=1'b1; #100 rst=1'b0;" and you should get a rst signal that is high for 100 ns, and then goes low again.
Assuming you use the default timescale of 1 ns, and assuming that code is in the initial block of your simulation.