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  1. #1
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    Regarding LVS Issue about mismatching ports

    hi every one

    In my LVS report I am getting an error as mismatched ports as follows.....

    Layout(gds) - 5005 ports

    Source (cdl) - 72 ports

    In my design there is only 72 ports....but the report shows there is 5005 ports...what is the reason for this???
    I have used a map file given in pdk document...Is there any problem in map file??? help me...

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    Re: Regarding LVS Issue about mismatching ports

    you need to work with CAD. The info you gave is very little to help. CALIBRE, ASSURA and HERCULES have a different methods of running LVS.



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  3. #3
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    Re: Regarding LVS Issue about mismatching ports

    hi....

    I am working with CALIBRE tool.....



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    Re: Regarding LVS Issue about mismatching ports

    in your report , there may be a discriptive summary .. please for any specific port copy paste the error messgages or info messages... Only then any of us can help u.

    - - - Updated - - -

    in your report , there may be a discriptive summary .. please for any specific port copy paste the error messgages or info messages... Only then any of us can help u.
    -Vlsi Expert



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    Re: Regarding LVS Issue about mismatching ports

    hi....

    I have attached detailed report ...



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  6. #6
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    Re: Regarding LVS Issue about mismatching ports

    As far as i could undertand the report, it clearly states that the objects that you have picked for schematic and layout is different. Moreover, it clearly states that the conectivity the routing is poor (Please dont mind). But, it very important to cross check with the schematic at early levels to avoid ending up at this stage. the report on page no "80" indicates that your MP (that is a PMOS has 5 ,pins both in schematic and layout). Well, i have never come across this 5 Legged/pins PMOS/NMOS whatever. SO kindly, have a relook at the design pick the same device/objects as you schematic. I mean it should coem from same family. If you are using mentoric station/cadence virtuoso, Kindly left click and and check the object properties. YOu will come to know the device family. Moreover naming convention is very important. I can see that you have created more ports in layout than schematic.

    So, it is advisable that kindly, check you schematic once again then go for layout and make it sure you rectify shorts and open problems in early schematic stage itself. So as to avoid getting such wierd results.


    Cheers.

    Check it once again, it not that a big deal.

    All the best.



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