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Systemverilog assertion ....

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shahsanket24

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hello to all....

i want to write the assertion in systemverilog for following condition
currently b=0 now whenever it changes it should be 2. b=0 may be for n number of clock cycle but whenever it changes it should be 2 i want to write property for this.

thanking you all.
 

shahsanket24 said:
hello to all....

i want to write the assertion in systemverilog for following condition
currently b=0 now whenever it changes it should be 2. b=0 may be for n number of clock cycle but whenever it changes it should be 2 i want to write property for this.

thanking you all.
Click to expand...

Code: 
 ap_b: assert property(@ (posedge clk)
                !$stable(b) && b==0 |=> b==2;  /// if unstable(b) and b==0, then @net cycle b==2
           );
--------------------------------------------------------------------------
Ben Cohen, Design and verification expert (310) 997-2187
https://www.systemverilog.us/ ben@systemverilog.us
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
--------------------------------------------------------------------------
 

Thanks for ur help...
Actually in my case b is varing between 0,1,2,3 but now what i actually want is after b=0 b has to be 2 whatever may be the no of clock cycle but once b changes it has to be 2 only b=0 can be for 5 clock cycle but what i want when b changes again it has to be 2.
 

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