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How to synthesis (VHDL) all GATE level digital circuit?

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isaacnewton

isaacnewton

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precision synthesis gate library

I am using Precision Synthesis to do VHDL design. Some time when I do synthesis, it doesn't give all gate level circuit.

Any one knows how to sysnthesis a digital circuit only with gates?

Thank you.
 

vhdl and gate

what else does the tool give you beside gates level ?
 

vhdl to gate

This does not happen to me.
 

-- Exampel - Thee following VHDL code is a simple MUX
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY MUX IS
PORT(in0, in1, in2, in3: IN std_logic;
S0, s1: IN std_logic;
z: OUT std_logic);
END ENTITY MUX;

ARCHITECTURE RTL OF MUX IS
BEGIN
z <= in0 WHEN s0 = '0' and s1 = '0' ELSE
in1 WHEN s0 = '0' and s1 = '1' ELSE
in2 WHEN s0 = '1' and s1 = '0' ELSE
in3 WHEN s0 = '1' and s1 = '1' ELSE
'0';
END ARCHITECTURE RTL;

-- The attached is synthesized circuit.
-- Thank you.
 

It's all gate level ! the right most device is a MUX.
 

dumeHCM said:
It's all gate level ! the right most device is a MUX.
Click to expand...

What I want is all INVERTER, NAND, NOR, XNOR ... gate circuit. Is it possible?
 

Your tool synthesize you code according to the basic library of primitive components. Either select your option or remove the primitive you doesn't like.
 

tochaHCM said:
Your tool synthesize you code according to the basic library of primitive components. Either select your option or remove the primitive you doesn't like.
Click to expand...

I can not find this kind of options. The tool I am using is
Precision Synthesis 2004a.74.

Thank you.
 

isaacnewton said:
dumeHCM said:
It's all gate level ! the right most device is a MUX.
Click to expand...

What I want is all INVERTER, NAND, NOR, XNOR ... gate circuit. Is it possible?
Click to expand...

Hi isaacnewton:

You can remove the basic cell you don't wanna from the lib, or you can

set the attribute of that cells to don't use.

wang1
 

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