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2.048 to 10 MHz clock multiplication...

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jay_ec_engg

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Hi friends..
I want to convert 2.048 MHz to 10Mhz... I have Spartan-3 device... Using DCM I am not able to get the exact factor for 10MHz.. I tried to search PLL also... but couldnt get anything... Can any one help me..
 

Hi,

How accurate do you want your 10 MHz clock, do you have to generate some kind of 1PPS signal or something....?

-maestor
 

I believe it is more easy to get 2.048 from 10MHz. You may get a 10Mhz clock from 2.048 clock. But it seems that it is hard to make the clock own better cycle and phrase. So could you tell something about your project and application? By the way, the clock acuracy is depent the source of clock,so how the 2.048 is and how the 10Mhz is.
 

clock sources are very accurate.. and I am planning to get multiplied clock to be very accurate... witth less than 10ppb....
i tried to get the same with cDCM of Xilinx.. I should get the factor 4.8828125 ( 10M/2.048M) ... but I found I can get 4.8( 24/5) with spartan-3.
any external PLL can do this ??

Do anyone have any idea??
 

Divide 2.048 MHz by 2048 via a counter to get a 1 kHz signal. Use this 1 kHz signal as a reference signal to a PLL, having a phaselocked 10 MHz VCO.
 

Message is unavailable.
 

I believe that the DCM can not work at this speed it is designed to work at 24 MHz minimum, so the DM can't be a nogotiable solution to such a design, an external PLL can do this or may be Lattice new FPGA contains an internal PLL but I dunno the clock speed it handles,

thats all folks
 

make by 10x multiplication of signal, to get 20.48MHz. then make DDS as:

if (clk'event and clk='1') then
acc<=acc+tune;
end if;

tune is tune word as: fout/20.48*2^N; where N is width of accumulator. use 24-32 bit precision. you'll hame some more jitter in signal, but the frequency can be quite precisious on longer scales :) 0.1-1Hz!

i forgot to add, how to get the clock out :) take MSB bit of accumulator, take it to BUFG driver and voila... :)
 

i read the last post, but if i am not worng Xilinx said in the DS that the minimum input frequency to lock the pll is 24 mhz.
If you would make a 10 mhz, not in FPGA from a 2040 you can use a cy22392 or similar.
whit a 2048 in you can have a 10mhz 0 ppm.
 

If you want a low-jitter output signal, you need an external PLL.
Even if the DCM would work at 2 MHz, it has some jitter.
The required PLL ratio is 625/128.
That Cypress chip sounds like a good candidate.
 

u can use DDS(direct digital synthesizer),which can give u any frequency u needed.
 

Hii Its really simple matter of mins USE LATTICE ISPCLOCK CHIP 5560 you will get the accurate output..
Bond
 

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