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How to write a script for synthesis

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ok i think i get the picture ... I am assuming u use DC if not tell me which tool u r using... this is a old synopsys tutorial ..dono why they discontinued giving it ... used it long back .. the source files required for this are still distributed by synopsys (never understand these EDA guys) .. ok

firstly
the source files may not exactly be in the same place as specified by the tutor ..but it will be there just search for it .. if u can't find it b'cos u r not well versed with unix ask ur friends for help .. ofcourse i can't help u from here ... there are a couple of slip ups ... if u r using verilog there is error while linking the source files

Second
If u want to learn synthesis through verilog ... there is a error in one of the verilog file ... one of the output in some module is not declared as reg ...(I don remember the exact file ..but when u try to compile .. it will tell u ) ... strange they haven't corrected it as yet .. If u still have problems contact me :)
 

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you‘d better learn from unix first so you can understand the advanced script programming.
 

I think first you should learn some basic unix commands ;second, you should understand the synthesis flow of DC;After that ,try to understand the commands in common use.

I don't think that you should start from GUI ,you can start from command line interface directly.Three months ago ,i have no idea about synthesis and dc.
But after red the boring sold ,I now can use dc and primetime skilly.

Be patient to read the sold ,you can get a lot from it finally.

Best wishes.
 

u may download the whole exampe from opencore.
include the code, script, and testbench etc.
 

can anyone tell how to write synthesis script for MAGMA
 

how can i begin with design compile if i have no foundry library?
 

patriot said:
how can i begin with design compile if i have no foundry library?
Click to expand...

Without a foundry libary you cannot compile the code to get a netlist...
If you want looking for a genric netlist.. you can use DC to genrate a GTECH Cell based netlist which has no timing information..

eg..
analyze file.v
elaborate Module_name
write -verilog gtech_netlist.v

BTW the std cell libraries can be freely downloaded from Artisan website..

rgds
 

I propose you should study the ic design flow and you can go to following Website
.....**broken link removed**
 

do a project with a team is the best way
 

I have a good script which was used in my Company please check it how we are following
 

vikasjn said:
ok i think i get the picture ... I am assuming u use DC if not tell me which tool u r using... this is a old synopsys tutorial ..dono why they discontinued giving it ... used it long back .. the source files required for this are still distributed by synopsys (never understand these EDA guys) .. ok

firstly
the source files may not exactly be in the same place as specified by the tutor ..but it will be there just search for it .. if u can't find it b'cos u r not well versed with unix ask ur friends for help .. ofcourse i can't help u from here ... there are a couple of slip ups ... if u r using verilog there is error while linking the source files

Second
If u want to learn synthesis through verilog ... there is a error in one of the verilog file ... one of the output in some module is not declared as reg ...(I don remember the exact file ..but when u try to compile .. it will tell u ) ... strange they haven't corrected it as yet .. If u still have problems contact me :)
Click to expand...

It is the DC tutorial 2000.05 form SOLD.
 

Synopsys's design compiler doc is a good start.
 

I think if you in a company as a project team member, the better way is to dig out the old scripts from past projects and raise a question to senior guys. And try to build a picture of chip works, most of the time you will get the good result, after you be familar with that tool, script is much convinient and timing saving.
 

goto www.tclforeda.org,

download a a sample synthesis script, and then modify it to for your design...analyze the results, keep tweaking it and you will learn much faster...it is a good way to start too docs are only for refernce...u cant learn synthesis by visual inspection or reading some stuff..
 

hi,you may see the help of the tools that you used,generally ,the help has the example of scripts
 

please upload some tcl script used for place and route.
 

check this blog

www.srikiran.net/blog/2007/01/12/logic-synthesis-primer/

Dont study the DC scripts...understand what your design requirements are...every designer will give you bare minimum requirements atleast...start with that...check what options you need and see how it affects ur design....etc..The above link will help you...
 

nice discussion here !

I think if u r able to get da basics rite n understand commands n their working thn its easy to do synthesis
Shiv
 

that is a good script！
 

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