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How to write a script for synthesis

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i suggest u make the basic timing acrs understood, such as input delay, setup time...etc, also the design environment: PVT, wire-load model, system interface characteristics.

then learn TCL syntax, just basic of operating variables, flow control ...etc

last, refer to the user guide of the systhesis tool u use
 

I think U want is how many items the scripts include.
1. firstly, I think is library. U should identify the trget library, link library, operation condition, wire load mode.
2. second, how do U know about Ur design. hierachy, each module, interface, bus, clock, func mode and test mode.
3. timing derate
4. how large Ur design is, and the method U will take?
 

go to this link:
dc_shell.html
or hit :"design compiler ug" in google searchbar.Down load design compiler ug1 to design compiler ug9 ..there would be many user guides but they are not useful and very high brow.Thats what i felt.Download these pdf.It is helping me very much.

-chandrakant
 

If your using Cadence for synthesis they ahve a command "write_template <options>" which exports a standard script that can used depeneding on the QoR target (area, timing, power etc) or any other key features. You only need to update it with your design input files (library, RTL etc) and use the script withing the tool.
 

HCM_bucat wrote

This book teach you alot about the scripts



Where is this?
 

tariq786

I just saw a post from the moderator quite a few days back. All books have been deleted.
 

Hello AndyJing,
above script did you write in perl for dc_shell.
 

If you are using Cadence RTL compiler, there is actually a command 'write_template' which will output synthesis script template to get you started.
Step 1: At unix prompt, type rc and enter
user@computer:rc
Step 2: After rtl compiler is launched, type 'write_template -full -outfile template.tcl'

Your synthesis script to get you started will be in template.tcl.
 

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