comparator with a single input

if a > b then
  output <= '1';
else
  output <= '0';
end if;

architecture count of counter is
  signal pre_count : integer;

begin
  
  process (clk, data)   --dont need to put enable in here, because you dont change anything when enable changes (you need a clock for things to change)
  begin
    if (data = '1') then  --are you sure you want data as your async reset?
      pre_count <= 0;
    elsif (clk'EVENT AND clk = '1') then
      if enable = '1' then
        pre_count <= pre_count + 1;
      
      --no need for an else here because it's registered and so holds its value implicitly
      end if;
    end if;
      
    
  end process;

  --outside the process
  count <= pre_count;

end count;

signal a : integer;

process(clk)
  variable b : integer;
begin
  if reset = '1' then
    a <= 0;
    b <= 0;
    
  if rising_edge(clk) then
    
    --variables
    op0 <= b;
    b := b + 1;
    
    op1 <= b;
    b := b + 1;
    
    op2 <= b;
    b := b + 1;
    
    --signals
    op3 <= a;
    a <= a + 1;
    
    op4 <= a;
    a <= a + 1;
    
    op5 <= a;
    a <= a + 1;    
    
  end if;
end process;

library ieee;
use ieee.std_logic_1164.all;
	

entity counter is
	port( 
		clk  : in std_logic;
		data : in std_logic;
		enable  : in std_logic;
	    count_one : out integer; 
		count_two : out integer
	);
end counter;

architecture count of counter is
	signal pre_count : integer;
	signal x : integer :=1 ;	
	
begin
	process (clk, data)
	begin
		if (data = '1') then
			pre_count <= 0;
		elsif (clk'EVENT AND clk = '1') then
			if enable = '1' then
				pre_count <= pre_count + 1;
			end if;
		end if;
	end process;
	
	process (data)
	begin
		if (data ='1') then
			if (x = 1) then
				count_one <= pre_count;
				x := 2;
			elsif (x=2) then
				count_two <= pre_count;
				x :=1;
			end if;
		end if;
	end process;
			
end count;

signal x : std_logic := '0';

process (clk)
begin
  if rising_edge(clk) then
	  
    x <= not x;
	  
    if x = '0' then
      count_one <= pre_count;
			
    else
      count_two <= pre_count;
			
    end if;
  end if;
end process;

signal data_sync : std_logic_vector(1 downto 0);

process(clk)
begin
  if rising_edge(clk) then
    data_sync <= data_sync(0) & data;
  end if;
end process;


count_proc : processs(clk)
begin
  if rising_edge(clk) then
    if data_sync(1) = '1' then
      count <= count + 1;
    end if;
  end if;
end process;

library ieee;
use ieee.std_logic_1164.all ;

entity delta is
   port (clk    : in  std_logic;
         din    : in  std_logic;
         dout  : out std_logic); 
end delta;
 
architecture rtl of delta is

signal q_s     : std_logic:='0';
signal clk_s   : std_logic;

begin
   process (clk)
    begin
        if rising_edge(clk) then  
            q_s <= din;
        end if ;
    end process ;
 
    clk_s <= clk;  -- delta delay!
 
   process (clk_s)
     begin
        if rising_edge(clk_s) then  
            dout <= q_s;
        end if ;
    end process ;
end rtl;