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There's no output enable in your design, it would need to use an inout port for the signal do. As is, a RAM instance can't be parallel connected which others.
As previously mentioned, FPGA have no internal bi-directional busses or tri-statable drivers. You can use tri-state in a behavioral design description, but it is converted to muxes by the design compiler. Thus using muxed directly is the clearer way to do it. I gave a mux example in post #39.
As previously mentioned, FPGA have no internal bi-directional busses or tri-statable drivers. You can use tri-state in a behavioral design description, but it is converted to muxes by the design compiler. Thus using muxed directly is the clearer way to do it. I gave a mux example in post #39.