How to fill a RAM using VHDL code?

Hi,

Yes. that controller part is already done. Only thing have to do with FPGA to control the BRAM to send the 8 bit output data to the 8 bit port one by one.? Just i have to switch the BRAM one by one to get the data. that is 1536 datas.

thanks,
V. Prakash

Hi,

Yes. As you suggest, i will go for a Mux to switch this RAMs

Please refer the attachment and Please check i am going in the right way.

********************************************
ENTITY MUX8_1 IS
PORT(DIN0:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DIN1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DIN2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DIN3:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DIN4:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DIN5:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DIN6:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DIN7:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX8_1;

ARCHITECTURE BEH123 OF MUX8_1 IS
BEGIN
PROCESS(DIN0,DIN1,DIN2,DIN3,DIN4,DIN5,DIN6,DIN7,SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DOUT<=DIN0;
WHEN"001"=>DOUT<=DIN1;
WHEN"010"=>DOUT<=DIN2;
WHEN"011"=>DOUT<=DIN3;
WHEN"100"=>DOUT<=DIN4;
WHEN"101"=>DOUT<=DIN5;
--WHEN"110"=>DOUT<=DIN6;
--WHEN"111"=>DOUT<=DIN7;
WHEN OTHERS=>
DOUT<="00000000";
END CASE;
END PROCESS;
END BEH123;

****************************************************
Please refer the rtl schematic for the above vhdl code


RAM1 output(8 bit Dout) is connected to DIN0(8 bit) of Mux input
RAM2 output(8 bit Dout) is connected to DIN1(8 bit) of Mux input
RAM3 output(8 bit Dout) is connected to DIN2(8 bit) of Mux input
RAM4 output(8 bit Dout) is connected to DIN3(8 bit) of Mux input
RAM5 output(8 bit Dout) is connected to DIN4(8 bit) of Mux input
RAM6 output(8 bit Dout) is connected to DIN5(8 bit) of Mux input
select lines will be controlled from the 3- bit counter to switch the RAM output.

Please correct me if i am wrong.

Thanks,
V. Prakash


https://obrazki.elektroda.pl/18_1320912179.jpg

The multiplexer is basically O.K., there are however much more open points,
- what commands RAM write and read rate?
- synchronization
- single shot or continuous operation intended
- definition of control signals in the schematic

Hi,

1) what commands RAM write and read rate?
Ans: Please refer the schematic of DVAL and LVAL Pulse, LVal =>(On time = 256 usec and Off time = 744 usec) continuously and Dval =>(On time = 0.5 usec and Off time = 0.5 usec ) continuously. These two pulses will be given to the External controller from FPGA.
For every falling edge of Dval, the one 8 bit data will be be send from the external controller to the FPGA and kept in FPGA RAM. The FPGA have to receive that data in the raising edge of that clock. DVAL and Clock to the RAM are the same. So, for every falling edge, one data will be send from External controller to FPGA and for every raising edge, that data will be received in the FPGA For 1 usec, one data. So for 256 usec, 256 datas will be received from controller to FPGA RAM.

6 RAMs in one FPGA will receive data from 6 different controllers parallely. Controllers and FPGA are synchronised with the clock of 1usec as i mentioned above.
For 256 Clocks, each clock = 1usec, the 6 RAMS of 256x8 will be filled from external controller. I have to send these datas in the order of RAM1 datas first, then RAM2, RAM3,RAM4, RAM5 and RAM6(totally 1536 datas) using the Multiplexer.

Multiplexer Select line --> 000 = RAM1 (256 Datas)
001 = RAM2 (256 Datas)
010 = RAM3 (256 Datas)
100 = RAM4 (256 Datas)
101 = RAM5 (256 Datas)
110 = RAM6 (256 Datas)


This Multiplexer and RAM have to be synchronised. For every 256 microsec, all RAMs will be filled parallely from controller. . I am planning to use 3-bit counter to choose this Select line. How to switch this select line within 256usec.? I have to send these total 1536 datas within 1ms to the 8 bit port.? Please give an idea for this?

2)synchronization?
Ans: As i mentioned above in 1st point Answer, Everything have to be synchronised. External Controller, RAM and Multiplexer.

3)single shot or continuous operation intended?
Ans : The operation is continuous. For Every 256usec, 6 RAMs have to be filled and same 1536 datas will be sent to the 8 bit port within 1ms. This will be happening continuously.

4) definition of control signals in the schematic?
Ans: As i mentioned in the 1st point Answer,1) Dval => On time= 0.5 usec, off time = 0.5 usec from FPGA to controller
2) LVal => On time= 256 usec, off time =744 usec from FPGA to controller
3) Clock to RAMs and Address counter of RAMs => 0.5 usec, off time = 0.5 usec
4) Clock to Multiplexer Select line 3-bit counter => ?

Please give an idea on this?

Thanks,
V. Prakash

https://obrazki.elektroda.pl/9_1320990884.jpg

Some progress at least.

For a clear specification, the timing diagram should be added and identical signal names used in block schematic and timing diagram.

I understand, that LVAL performs the input data synchronization (should be clarified as well), but I guess, that the input part is clear so far.

The output (FPGA to PC) timing and synchronization hasn't been mentioned yet. It's required to transmit 6*256 Bytes per ms for continuous operation, so there must be a faster clock. I would rather expect the read timing controlled by the PC. But how?

Hi,

1)LVAL performs the input data synchronization
Yes..

2) My part is to transmit 6*256 Bytes per 1 ms through that 8 bit port. In PC side, they are planning to use DIO card to receive the data in PC.
In PC side --> 8 bit data port and same 1 usec clock

For every falling edge of Dval, the one 8 bit data will be be send from the external controller to the FPGA and kept in FPGA RAM. The FPGA have to receive that data in the raising edge of that clock and PC will receive the data in the falling edge of that same clock.

My part is to transmit 6*256 Bytes per 1 ms through that 8 bit port from FPGA continuously. We can achieve this? Please let me know and Please help on this.

Thanks,
V. Prakash

I calculate 6*256 = 1536. So how do you transmit it in 1 ms with 1 µs clock period? That's why I said, there must a faster clock. It's a simple specification problem.

Hi,

Yes. For 1 usec clock, => 6 rams x 256usec = 1536 usec that is, 1.53ms for total 1536 datas.
We can reduce that clock as 0.5usec,=> 6 rams x 128us = 768 usec that is, 0.768 ms for total 1536 datas.
Within 1msec, i have to send this 1536 datas. So, we can achieve this in 0.5 us clock.

Yes. as you told, we can change the clock frequency for faster clock. that is no issues. we can achieve this? Please correct me if i am wrong?

thanks,
V. Prakash

we can change the clock frequency for faster clock

Click to expand...

Yes, I suppose so. It's a necessary supplement to the specification. You also need to consider, when to start transmission of first RAM word. You'll possibly get data from different frames send to the PC because new data are stored to the RAM while sending. If it's unwanted, the send clock rate and start time must be adjusted respectively. Or double buffering to be implemented.

Sometimes I'm remembered to the proverb bearing the dog for hunting.

Hi,

Double buffering in the sense, it is two RAMs instead of one RAM? In one RAM i will fill the datas and in the another ram i will send the data to the 8 bit port with faster clock? so totally i have to use 12 RAMS instead of that 6 RAM? am i right?
Please let me know.

Thanks,
V. Prakash

Hi,

VHDL code for Dual port RAM:
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram_simple IS
PORT (
SIGNAL data : IN std_logic_vector(7 DOWNTO 0);
SIGNAL address : IN std_logic_vector(4 DOWNTO 0);
SIGNAL we, inclock, outclock : IN std_logic;
SIGNAL q : OUT std_logic_vector(7 DOWNTO 0));


END ram_simple;


ARCHITECTURE fe2 OF ram_simple IS

TYPE mem_type IS ARRAY ( 31 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
SIGNAL address_int : unsigned(4 DOWNTO 0);

BEGIN -- ex2
l0 : PROCESS (inclock,outclock, we, address)

BEGIN -- PROCESS
IF (inclock = '1' AND inclock'event) THEN
address_int <= unsigned(address);
IF we = '1' THEN
mem(To_integer(unsigned(address))) <= data;
END IF;
END IF;
IF (outclock = '1' AND outclock'event) THEN
q <= mem(to_integer(address_int));
END IF;

END PROCESS;

END fe2;
----------------------------------------------

Please clear this. Please refer the RTL Schematic for the Dual Port RAM attached.

In this Dual Port RAM , We have two Clocks which is, inclock and outclock.

1)
For 1st inclock --> 1st data will be placed --> with addressA 0000 0000 (using 8-bit address counter)
For 2nd inclock --> 2nd data will be placed --> with addressA 0000 0001 (using 8-bit address counter)
For 3rd inclock --> 3rd data will be placed --> with addressA 0000 0010 (using 8-bit address counter )
"
"
"
"
For 255th inclock --> 255th data will be placed --> with addressA 1111 1111 (using 8-bit address counter )

Now the RAM gets filled using inclock. condition: Write Enable = '1' . Now the RAM filling portion is over.

2)
Then i have to send these filled datas out. For this to be done, outclock is used.
Condition : Write Enable = '0'

For every outclock, one data will be send to the out port with which address location? What is the Role of this D- Flipflop(FD) in the
RTL Schematic for AddressB? Can you please let me know this.

After the filling the ram, that is, after 255th inclock , what will be the address in the AddressB(7:0)?
Please let me know the role of this D FlipFlop.? Please help me.

Thanks,
V. Prakash

https://obrazki.elektroda.pl/8_1321248218.jpg

---------- Post added at 10:55 ---------- Previous post was at 10:55 ----------

Hi,

VHDL code for Dual port RAM:
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram_simple IS
PORT (
SIGNAL data : IN std_logic_vector(7 DOWNTO 0);
SIGNAL address : IN std_logic_vector(4 DOWNTO 0);
SIGNAL we, inclock, outclock : IN std_logic;
SIGNAL q : OUT std_logic_vector(7 DOWNTO 0));


END ram_simple;


ARCHITECTURE fe2 OF ram_simple IS

TYPE mem_type IS ARRAY ( 31 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
SIGNAL address_int : unsigned(4 DOWNTO 0);

BEGIN -- ex2
l0 : PROCESS (inclock,outclock, we, address)

BEGIN -- PROCESS
IF (inclock = '1' AND inclock'event) THEN
address_int <= unsigned(address);
IF we = '1' THEN
mem(To_integer(unsigned(address))) <= data;
END IF;
END IF;
IF (outclock = '1' AND outclock'event) THEN
q <= mem(to_integer(address_int));
END IF;

END PROCESS;

END fe2;
----------------------------------------------

Please clear this. Please refer the RTL Schematic for the Dual Port RAM attached.

In this Dual Port RAM , We have two Clocks which is, inclock and outclock.

1)
For 1st inclock --> 1st data will be placed --> with addressA 0000 0000 (using 8-bit address counter)
For 2nd inclock --> 2nd data will be placed --> with addressA 0000 0001 (using 8-bit address counter)
For 3rd inclock --> 3rd data will be placed --> with addressA 0000 0010 (using 8-bit address counter )
"
"
"
"
For 255th inclock --> 255th data will be placed --> with addressA 1111 1111 (using 8-bit address counter )

Now the RAM gets filled using inclock. condition: Write Enable = '1' . Now the RAM filling portion is over.

2)
Then i have to send these filled datas out. For this to be done, outclock is used.
Condition : Write Enable = '0'

For every outclock, one data will be send to the out port with which address location? What is the Role of this D- Flipflop(FD) in the
RTL Schematic for AddressB? Can you please let me know this.

After the filling the ram, that is, after 255th inclock , what will be the address in the AddressB(7:0)?
Please let me know the role of this D FlipFlop.? Please help me.

Thanks,
V. Prakash

https://obrazki.elektroda.pl/8_1321248218.jpg

---------- Post added at 11:06 ---------- Previous post was at 10:55 ----------

HI,

sorry. that vhdl code has 32x8 ram. For my application, it is 256x8: Please refer this code for the above attached RTL schematic

ENTITY ram_simple IS
PORT (
SIGNAL data : IN std_logic_vector(7 DOWNTO 0);
SIGNAL address : IN std_logic_vector(7 DOWNTO 0);
SIGNAL we, inclock, outclock : IN std_logic;
SIGNAL q : OUT std_logic_vector(7 DOWNTO 0));


END ram_simple;


ARCHITECTURE fe2 OF ram_simple IS

TYPE mem_type IS ARRAY (255 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
SIGNAL address_int : unsigned(7 DOWNTO 0);

BEGIN -- ex2
l0 : PROCESS (inclock,outclock, we, address)

BEGIN -- PROCESS
IF (inclock = '1' AND inclock'event) THEN
address_int <= unsigned(address);
IF we = '1' THEN
mem(To_integer(unsigned(address))) <= data;
END IF;
END IF;
IF (outclock = '1' AND outclock'event) THEN
q <= mem(to_integer(address_int));
END IF;

END PROCESS;

END fe2;
----------------------------------------------

thanks,
V. Prakash

Then i have to send these filled datas out. For this to be done, outclock is used.
Condition : Write Enable = '0'

Click to expand...

With a dual port RAM, read and write is basically independent. In your design, you have used a common address input for read and write port, but it's not a necessary condition.

What is the Role of this D- Flipflop(FD) in the RTL Schematic for AddressB.

Click to expand...

It's implented according to the additional address register in your code, but not generally required, I think. (I'm not familiar with Xilinx RAM interference rules).
address_int <= unsigned(address);

After the filling the ram, that is, after 255th inclock , what will be the address in the AddressB(7:0)?

Click to expand...

You have to apply a sequence of read addresses, similar to the write addresses before.

Hi,

With a dual port RAM, read and write is basically independent. In your design, you have used a common address input for read and write port, but it's not a necessary condition.

Click to expand...

1) For dual port, inclock to write into the ram and outclock to read the ram.
while writing into the RAM --> i will give clock pulse to the inclock, we ='1' and 8 bit address counter with same clock as inclock and no clock pulse to outclock.
while reading the RAM --> i will give clock pulse to the outclock, we='0' and 8 bit address counter with same clock as outclock and no clock pulse to inclock. correct?

2) if i have to read the RAM faster means, i will keep the outclock faster than the inclock. For this, i have to use two different address counter for read and write? correct? For writing into the RAM with 1usec clock and reading the RAM with 0.5usec clock need the two different address counter.?
Common clock to inclock and 8 bit address counter clock (clock = 1 usec) --> for writing into the RAM
Common clock to outclock and 8 bit address counter clock (clock = 0.5 usec) --> for reading the ram
Please correct me if i am wrong?

Please refer the RTL schematic with two different address port for writing and reading the RAM. this dual port ram will occupy the space as two different 256x8 bram in the design or single 256x8?


Thanks,
V. Prakash

https://obrazki.elektroda.pl/51_1321261153.jpg

The design can work as described, I think.

I'm not sure about Xilinx. Normally block RAM occupies the same space, either used as single or double port RAM.

Hi,

Ok. i will design the Same and let you know.

Thanks,
V. Prakash

Hi,

Can we connect two BRAM( 1st BRAM Data_out(7:0) and 2nd BRAM Data_out{7:0)) outputs together using the signal? Please let me know.

thanks,
V. Prakash

FPGAs don't have true internal tri-state signals. Consequently, the RAM blocks don't expose an output enable signal and the outputs are permanently enabled. To combine the different RAM channels, you need a multiplexer, e.g. a simple conditional assignment statement like this
or a respective sequential statement in a process.

Hi,

Please look at this:
*********************************
entity ram is
port (clock : in std_logic;
we : in std_logic;
a : in std_logic_vector(7 downto 0); --4 downto 0
di : in std_logic_vector(7 downto 0); --3 downto 0
do : out std_logic_vector(7 downto 0);
OE : in std_logic);

end ram;

architecture syn of ram is
type ram_type is array (255 downto 0)
of std_logic_vector (7 downto 0);
signal RAM : ram_type;

begin
process (clock)
begin
if (clock'event and clock = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di; --"10101010"; --di
end if;
end if;
if (OE = '1') then
do <= RAM(conv_integer(a));
end if;
end process;
end syn;
***********************************

In this RAM code, i had just added the output enable control (OE). Can we do like this to have a OE control.?
Please look at this RTL Schematic. Please let me know.


Thanks,
V. Prakash

https://obrazki.elektroda.pl/99_1321520928.jpg

do you want the output enable clocked or tri-stated? either way, you have not got it in the correct place. You need to move it inside the clock branch if you want it synchronous or outisde the process (or in another process) if you want it tri-stated.

Hi,

Yes. it is to be tristated. I have to write into the ram location using write enable. and i have to read data out using OE.

Please check this one. OE placed inside the process.

entity ram is
port (clock : in std_logic;
we : in std_logic;
a : in std_logic_vector(7 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
OE : in std_logic);

end ram;

architecture syn of ram is
type ram_type is array (255 downto 0)
of std_logic_vector (7 downto 0);
signal RAM : ram_type;

begin
process (clock)
begin
if (clock'event and clock = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di; --"10101010"; --di
elsif (OE = '1') then
do <= RAM(conv_integer(a));
end if;
end if;
end process;
end syn;

Please refer the schematic attached for the VHDL Code.

Thanks,
V. Prakash

https://obrazki.elektroda.pl/87_1321591236.jpg