allennlowaton
Full Member level 5
Hello EDA fellows,
Please help me on how to implement a nested/hierarchical subcircuit on the source netlist in the Cadence LVS check.
My source netlist goes like this;
.subckt name1 param1 param2
.subckt name2 param3 param4
** content***
.ends
.subckt name3 param5 param6
**content***
.ends
x1 param3 param4 name2
x2 param5 param6 name3
.ends
After LVS check, an error message "Source netlist references but does not define (2) subcircuits. name2 name3"
Hope anyone out there can give solution on this.
Thank you.
Please help me on how to implement a nested/hierarchical subcircuit on the source netlist in the Cadence LVS check.
My source netlist goes like this;
.subckt name1 param1 param2
.subckt name2 param3 param4
** content***
.ends
.subckt name3 param5 param6
**content***
.ends
x1 param3 param4 name2
x2 param5 param6 name3
.ends
After LVS check, an error message "Source netlist references but does not define (2) subcircuits. name2 name3"
Hope anyone out there can give solution on this.
Thank you.
Last edited: