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[SOLVED] hierarchical and multiple subcircuit call on source netlist in Cadence LVS check

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allennlowaton

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Hello EDA fellows,

Please help me on how to implement a nested/hierarchical subcircuit on the source netlist in the Cadence LVS check.
My source netlist goes like this;

.subckt name1 param1 param2

.subckt name2 param3 param4
** content***
.ends

.subckt name3 param5 param6
**content***
.ends

x1 param3 param4 name2
x2 param5 param6 name3

.ends


After LVS check, an error message "Source netlist references but does not define (2) subcircuits. name2 name3"

Hope anyone out there can give solution on this.

Thank you.
 
Last edited:

Try:

.subckt name2 param3 param4
** content***
.ends

.subckt name3 param5 param6
**content***
.ends

.subckt name1 param1 param2
**content***

x1 param3 param4 name2
x2 param5 param6 name3

.ends

i.e. don't define subcircuits within subcircuits.

Keith.
 
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