the_falcon
Member level 4
hi all,
I am trying to design a differential comparator in which i have a differential input stage, then two cmos flip flops.my differential amplifier is actually having a differential PMOS input pair biased by PMOS current mirror of the ratio of 1:2 and its directly connected to the flip flop section.
what bothers me is , is there any way for me to have the gain from the differential input stage if i directly connect it to flip flop section without having any kind of load at the output of the input PMOS pair
i am attaching the technical paper i referred, here.please help me out in this
falcon
I am trying to design a differential comparator in which i have a differential input stage, then two cmos flip flops.my differential amplifier is actually having a differential PMOS input pair biased by PMOS current mirror of the ratio of 1:2 and its directly connected to the flip flop section.
what bothers me is , is there any way for me to have the gain from the differential input stage if i directly connect it to flip flop section without having any kind of load at the output of the input PMOS pair
i am attaching the technical paper i referred, here.please help me out in this
falcon
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