Instruction cycle, machine cycle

please correct me if i am wrong

1)clock cycle is the period of the input clock

2)Instruction cycle= time taken to fetch+decode+execute+write back
But due to pipelining we can somehow make instruction cycle = fetch = decode = execute = write back

3)Machine Cycle= time taken to perform a memory access operation
For CISC the complex instructions perform 'many' memory operations so instruction cycle='many' machine cycles
For RISC the simple instructions perform 'one or two' memory operations so instruction cycle='one or two' machine cycles

4)T-states= one machine cycle takes many clock cycles called t-states?????
dont know how the t-states are reduced...:???:

I am learning so I may be completly wrong, so sorry for that..... all the above is an effort to find out why avr executes one instruction per clock cycle

Among above, clock cycle, and maybe instruction cycle as well, is the only one universally recognized. The rest probably depends on who you ask, or which book you read.