program
Junior Member level 2
Hi every one
I am calculating Area, power and timing in ASIC using Synopsys Design Compiler and ModelSim. After Anlyzing and elaborating the design then applying constraint and Compiling, I saved the sdf file (using Design Compiler) as follow:
write_sdf ./SYNOPS/SOURCE/test_defult.sdf
when I use ModelSim Command:
vsim -sdfmax /kkk_tb/uut=./SYNOPS/SOURCE/test_default.sdf work.kkk_tb
I got the following Errors:
** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/test_default.sdf(60): Failed to find INSTANCE '\output_reg[0] '
.
.
.
** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/test_default.sdf(57): Failed to find INSTANCE '\x0_reg[0] '.
Please any suggestion ??
thanks
I am calculating Area, power and timing in ASIC using Synopsys Design Compiler and ModelSim. After Anlyzing and elaborating the design then applying constraint and Compiling, I saved the sdf file (using Design Compiler) as follow:
write_sdf ./SYNOPS/SOURCE/test_defult.sdf
when I use ModelSim Command:
vsim -sdfmax /kkk_tb/uut=./SYNOPS/SOURCE/test_default.sdf work.kkk_tb
I got the following Errors:
** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/test_default.sdf(60): Failed to find INSTANCE '\output_reg[0] '
.
.
.
** Error: (vsim-SDF-3250) ./SYNOPS/SOURCE/test_default.sdf(57): Failed to find INSTANCE '\x0_reg[0] '.
Please any suggestion ??
thanks