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opamp outputs a high signal even when the input is 0

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sherazi

sherazi

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i am using this circuit , and the problem i am facing is that sometimes when the input is becomes enough to make the output high and then gets to 0 value the opamp still outputs a high value, is there any way to ensure that ouput comes to 0 after the input has gone low...

the circuit is for a vibration sensor, and the input is induced in the coil via a vibrating magnet on the spring ...
57875d1309064891-untitled.png
 

There are multiple design faults present in your circuit.
- The first stage should be preferably biased as a linear amplifier.
- The second stage has positive feedback and is latching the previous state indpendent of an input signal, but not working as an amplifier.
 

L2 is the input source actually ...
and the problem is in first stage as its output stays high even when the i/p is low again.
but when a new pulse comes its ok again.
the problem i am facing is that some times the O/p LED wont stop glowing after a pulse is low again .its not always like this but still quite a few times and after another pulse the led will go off after the pulse is finished ...
 

Why didn't you comment on the 2nd stage (as FvM suggested)?
Why don't you show us the power supply (supplies?) for the 1st stage? It is important to know if single or double supply!
 

Why don't you show us the power supply (supplies?) for the 1st stage? It is important to know if single or double supply!
Click to expand...
They are shown - and single supply, because both OPs shares the supply pins.
and the problem is in first stage as its output stays high even when the i/p is low again.
but when a new pulse comes its ok again.
the problem i am facing is that some times the O/p LED wont stop glowing after a pulse is low again .its not always like this but still quite a few times and after another pulse the led will go off after the pulse is finished ...
Click to expand...
The latching behaviour is caused by the positive feedback, as said. The first stage, if the real circuit is wired according to the schematic, has a low output voltage in idle state.
 

FvM said:
They are shown - and single supply, because both OPs shares the supply pins.
Click to expand...

Hard to detect. In this case (single supply), I doubt how the 1st stage will find a proper bias point.
 

Hard to detect.
Click to expand...
It's clear, if you have the LM358 pin assignment in mind.
I doubt how the 1st stage will find a proper bias point.
Click to expand...
According to the common mode range of LM358, it will work as a half-wave rectifier with gain. Depending on the individual LM358 offset voltage, low level signals may be suppressed. Although this operation mode isn't reasonable at all, the first stage still passes an input signal.

Second stage operation however is messed up by the (most likely erroneously implemented) positive feedback.
 

When I use LM358, I try not to let its input go below 300mV (to have a good margin before a possible latch up). In this circuit, L2 via C5 may drive the positive input below 700mV at which the output may be undetermined or be latched to a high state. Since I am not sure what could be the amplitude of the maximum negative voltage and current at IN+, I suggest to add a series resistor (10K to 100K) to it (IN+) which helps reducing its negative current hence avoiding latching.

Added:
For instance, for a negative voltage at the input (IN+ and/or IN- and between 0 and -300mV), LM358 (and LM324) runs in its linear region.
 
Last edited:

When I use LM358, I try not to let its input go below 300mV (to have a good margin before a possible latch up). In this circuit, L2 via C5 may drive the positive input below 700mV at which the output may be undetermined or be latched to a high state.
Click to expand...
It's a good point to consider possible latch-up. According to the datasheet, it can be excluded for the present circuit however. It specifies a maximum clamp diode current of 50 mA and states about the expectable behaviour in note 3:
This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors
becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the
IC chip. This transistor action can cause the output voltages of the op amps to go to the V+voltage level (or to ground for a large overdrive) for the time duration that
an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value
greater than −0.3V
Click to expand...
In other words, polarity reversal can be expected, latch-up shouldn't happen. The AC coupling prevents larger clamp current even in the case of higher input voltages. In the present case, the moving magnet won't hardly be able to supply it, however.

I understand that you are talking about negative voltage levels when considering margins.
 

i have tried using a Rc compensating resistor at noninverting input .. but the output is still high ... when i use DMM to check o/p of both stages , i see that whenever latching takes place the o/p of the 1st stage is still in its high value as it used to when spring vibrates
 

Is R11=620R or 620K?

What is the value of C6?

Just to be sure, did you insert a resistor between pin5 and C6? If you did what was its value?
 

i have tried using a Rc compensating resistor at noninverting input
Click to expand...
Don't what it is or what it's good for.

The first stage should have an input bias, that sets the output voltage to mid range without an input signal. The second stage should be changed to negative feedback, by permuting pin 2 and 3.

You can either continue to perform arbitrary circuit modifications, or refer to the basics of OP circuit design.

P.S.: If the output of the first stage (pin 7) doesn't return to low level, something is broken or wired different from the schematic. Pin 4 may however latch arbitrarily at high or low.
 

The first stage should have an input bias, that sets the output voltage to mid range without an input signal.

Yes, therefore my doubts regarding operating point (my posting yesterday).
It's surprising that sherazi does not react on comments to his 2nd stage.
 
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    FvM

    FvM

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r11 =620 Ohm, C6 is 0.1uF, No resistor b/w 5 and 6.

iN the second stage VR is 4.5Mohm used for sensitivity selection , its in feedback loop if the input of second stage is less than 2.5V the output is low ,if it becomes higher then the o/p is high
 

sherazi said:
iN the second stage VR is 4.5Mohm used for sensitivity selection , its in feedback loop if the input of second stage is less than 2.5V the output is low ,if it becomes higher then the o/p is high
Click to expand...

Question: Is VR simply a variable resistor without connection to ground at its lower end (as shown in the diagram) or does it act as voltage divider?
 

Assuming, the original cicruit has been working, I would double check the schematic against the PCB first. I already made my suggestions.
 

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