what is about symbol library in Design-vision?

You can get a symbol library from the Asic Vendor or you can generate a symbol library yourself.

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Actually, Library Compiler has to be used to convert both the tech.file(.lib) and symbol library(.slib) to .db and .sdb respectively.

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kermit said:

wadaye:

You can get a symbol library from the Asic Vendor or you can generate a symbol library yourself.

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How to generate a symbol library by myself? can you give more detail information about this? Or you can give me some reference documents about this in SOLD!


giggs11

Actually, Library Compiler has to be used to convert both the tech.file(.lib) and symbol library(.slib) to .db and .sdb respectively.

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where can i get symbol library .slib?Vendor provide?
But I can't find this in UMC 0.25 CMOS library.

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If foundry do NOT provide slib, you might find it in synopsys CD.

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How to convert an EDIF schematic symbol library to synopsys .slib


Question:


How do I convert an EDIF schematic symbol library to synopsys .slib?
Answer:


dc_shell> read_lib EDIF_filename -format edif -symbol symbol_filename.slib

EDIF_filename is the EDIF file containing symbol information generated by EDIFOUT.

symbol_filename.slib is the ASCII file that will contain the Synopsys
version of the symbol library.

In addition, set all neccessary edifin variables( refer to EDIF
Interface User Guide, and all edifin_lib variables):

edifin_lib_route_grid = 1024
1024
edifin_lib_in_port_symbol = "ipin"
"ipin"
edifin_lib_out_port_symbol = "opin"
"opin"
edifin_lib_inout_port_symbol = "iopin"
"iopin"
edifin_lib_in_osc_symbol = "iosc"
"iosc"
edifin_lib_out_osc_symbol = "oosc"
"oosc"
edifin_lib_inout_osc_symbol = "oosc"
"oosc"
edifin_lib_logic_0_symbol = "gnd"
"gnd"
edifin_lib_logic_1_symbol = "vdd"
"vdd"
Former article name: METH-844

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Converting modeldb to ITS (.slib) Models


Question:


Can PathMill convert an existing modeldb to a ITS (.slib) timing model?


Answer:


Yes, you can do this in two ways.

1. Using PathMill Plus to read in the modeldb file and then write out the same
model in ITS (.lib) format.

a. In PathMill Plus batch mode:
1) Include these TCL commands in your command file to read your modeldb file
and then write it out in the format (STAMP | ASCII | ITS) you desire.

read_model -format modeldb -name { model.modeldb }
write_model -format ITS -name its_model_name

2) Run PathMill Plus (converts model).

If you happen to have more than one model, you can also merge these into a final
ITS (.lib). In your command file include these commands to read, select paths,
and write out the model:

read_model -format modeldb -name { model1.modeldb }
read_model -format modeldb -name { model2.modeldb }
mark_model_paths -select -mode MODE1 MODE2
write_model -name ALL -format ITS -modes MODE1 MODE2

Note: It is assumed that model1.modeldb and model2.modeldb above are generated
with a specific mode (MODE1 and MODE2, respectively). The "-select" option
selects paths in nonoverlapping fashion. The write_model command writes all
modes to a single database in ITS format.

b. In PathMill Plus mg or model editing (shell) mode (invoke PathMill -mg
shell):

shell> pathmill -plus -mg -tcl
mg>read_model -format modeldb -name model_name.modeldb
mg>write_model -format ITS -name its_model_name

In mg mode, you can also use the previously described methods to merge models
into a final ITS (.lib) when you have more than one model to be read.

2. The second way is to generate an ITS (.lib) model for a dummy module
containing only the model you want to convert. For this conversion, we'll
use the build_model config command with options "syn_lut syn_its" to create
a ITS (.lib) model from the .modeldb file.

a. Read the circuit containing the modeldb (for example, adder.modeldb); for
example,

pathmill -nspice model.sp netlist.top \
-c cfg \
-o adder \
-x

model.sp contains a dummy module declaration and netlist.top is tx-level
netlist for the block.

.subckt top port-list...
X1 port-list... adder
.ends

Where "adder" is the prefix in timing model name we have.

Also, you will need to use these config commands to set netlist control
options to read the modeldb and generate a new ITS model in PathMill;
for example,

netlist_ctrl_opt prefer_model_port_map:"adder.modeldb"
build_model model_name syn_its syn_lut charfile ....

Note: Here you would also provide characterization data. The charfile used
in this run should match the one used when creating the original modeldb file.
If this data is not provided for a given input or output port:

* PathMill finds the input slope from the default_rf_time and the output
capacitance from the sink_node commands.

* Characterization is performed by varying slope or capacitance (0.5, 1, 2)
times the default_rf_time and the output capacitance from the sink_node
commands.


Note: If your models are in SASCII format, you will need to convert them to
modeldb format by using PathMill. Different versions of PathMill may have
different binary formats.

You will get a WARNING message if the binary file is incompatible with the
version you're using. To convert timing databases from major release to release,
use the same PathMill version that was used to generate the binary database to
convert it to ASCII format first. Then use current version of PathMill to
convert from ASCII to binary format. To convert from ASCII to binary format
or visa versa, use the following options:

pathmill -ascii2modeldb model.ascii model.modeldb
pathmill -modeldb2ascii model.modeldb model.ascii

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