what's the problem of the following systemverilog code?

Can anyone please help tell me what's the problem of the following systemverilog code?

The values on "a/b/c" of interface instance are all X value.

interface intf(input clk);
logic [7:0] a;
logic [7:0] b;
logic [7:0] c;

modport driver(output a, output b, input c, input clk);
modport receiver(input a, input b, output c, input clk);
endinterface

module tb;


class Driver;
virtual intf.driver port;

function new (virtual intf.driver port);
this.port = port;
endfunction

task run;
int i = 0;
while (i < 10) begin
port.a <= i;
port.b <= i;
i = i + 1;
@(posedge port.clk);
end
endtask

endclass

class Receiver;
virtual intf.receiver port;

function new (virtual intf.receiver port);
this.port = port;
endfunction

task run;
fork
while (1) begin
@(posedge port.clk);
port.c <= port.a + port.b;
end
join
endtask

endclass

bit clk = 0;

intf u_intf (.clk(clk));


initial begin
forever #5 clk += 1;
end
Driver drv;
Receiver rcv;

initial begin
drv = new(u_intf.driver);
rcv = new(u_intf.receiver);
rcv.run;
drv.run;

repeat(100) @(posedge clk);
$finish;
end

endmodule

---------- Post added at 23:22 ---------- Previous post was at 23:16 ----------

It seems the problem existed within the interface instance. I tried that when "rcv.run" is not called, just "c" has X value, "a" and "b" are correct values.

you'd better to control rcv and drv start flow!

ljxpjpjljx said:

you'd better to control rcv and drv start flow!

Click to expand...

yes, the problem is fixed by fork two process of rcv and drv run.

Thank you.