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Issue with Quartus II SignalTap II

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highstreets

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Hi guys, I have compiled my VHDL coding in Quartus II and proceeded to SignalTap for simulation. However, when I tried to click 'run analysis' button under 'Processing' tab in SignalTap II Logic Analyzer each time it generates a new waveform.

I have verified my design in Modelsim and it works fine. Now I'm trying to implement my design into FPGA board and see if it matches.

Please help. Many thanks.
 

You didn't tell why you assume the same waveform (reproducable combination of input signals, trigger conditions).
 

The design I'm working on will generate a periodic sine wave. That's why I'm assuming the results that I got from both simulators should be the same.
 

I don't exactly understand how you are applying SignalTap II. It's a debugger rather tha a simulator. To check for possible timing issues and other constructs that don't work in synthesis, you can perform a gate level simulation of the routed design with ModelSim.
 
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