Please see the system showing in figure1.
System background: Itís used in wireless digital repeater including local unit and remote unit. And there are 2 different reference clocks in whole system, so it will cause the system output frequency offset badly if the 2 clocks (e.g. TCXO ) exist large frequency stability.

Phenomenon description: In the lab, signal generator is input into ADC, and through the whole system the signal is output to spectrum analyzer. But the signal is shaking in frequency domain.

My analysis and target: Through some experiments (e.g. increase TCXO temperature, the phenomenon will deteriorate), the phenomenon is confirmed that itís caused by different clocks. And my target is to get it into normal through DSP realized in FPGAóbring the frequency offset into normal index.
So far, I have tried to search some papers on digital costas loop. In the lab, I found that the loop could be locked in local unit or remote unit separately, but when I connected two parts the loop cannít be locked.

Question: Is there any other solution to such problem except costas loop, if costas loop is the exact one, could you give me some advice on it?

PS: I am just working on the loop with CW signal, not modulation.

attachement: Figure 1 system used in wireless digital repeater