allennlowaton
Full Member level 5
good day EDA fellows..
I had this question in mind.
As stated in the title, what are the possible effects of having a higher than Vdd clock to MOS (a switch) of a charge pump circuit.
thanks.
I had this question in mind.
As stated in the title, what are the possible effects of having a higher than Vdd clock to MOS (a switch) of a charge pump circuit.
thanks.