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effects of having a higher than Vdd clock to MOS (a switch) of a charge pump circuit

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allennlowaton

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good day EDA fellows..
I had this question in mind.
As stated in the title, what are the possible effects of having a higher than Vdd clock to MOS (a switch) of a charge pump circuit.
thanks.
 

allennlowaton

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But I also have PMOS. What are the possible effects on them?
 

leo_o2

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Pls post your schematic for further analysis. Chargepump will boost some node voltage higher than Vdd, so it needs the voltage higher than Vdd to turn off PMOS completely?
 
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