miracle123
Newbie level 4
Can I implement a circuit from truth table in Xilinx ? If so, how ?
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity truth_table is
port ( input :in std_logic_vector(2 downto 0);
output :out std_logic_vector(2 downto 0)
);
end truth_table;
architecture Structural of truth_table is
begin
output <= "000" when input="001"
else "011" when input="010"
else "111" when input="100";
end Structural;