designing a common source amplifier with a certain gain

I need to desing a simple common source amplifier with only one resistor (Rd) and using a Vdd of at most 3.3 V. Moreover, I need to obtain 10 gain. I'm trying to amplify a 10 mV signal at 1 MHz freq. As a load a 50 fF capacitor is connected.
I tried various Vdd and resistance values, but I can't seem to get a gain larger than 5-6. My signal has a 1 V DC bias. What should be the appropriate solution here to get a gain of 10. This is like a first design in Cadence, I'm using a transistor called nmos4 and I have no idea about its W/L values and thus I can't do any calculations to find Id, gm and the gain. So, I just tried out some resistor values and changed my Vdd ranging up to 3.3 V, but still I'm not sure how the gain is affected. I know the basic theory behind the CS amplifier but can't apply it in this case. Any suggestions or tips?
Thanks..

Cadence enables u to change th W/L for sure... and when u do the simulation u can select to ouput the current so u can easily no what is Id

You need to find a transistor that has a greater ΔRds/ΔUg (can't remember the english word for this property of fet) to be able to amplify that much.

Either that, or you can cheat a little by inserting an opamp with negativefeedback from output. But that will affect the amplifier high freq properties.

Read som stuff here.