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DRC Error: AMTS1 max. MTOP spacing ...

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crigri

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Hi!

I did a layout for a digital interface. Then i imported it back to virtuoso and i did the DRC.

It stated that:
AMTS1 maximum MTOP spacing when the width of one or both MTOP shapes is less than 10um = 10


MTOP is in this case metal4 and the gap between two wires exceeds sometimes 10um. But is this really a problem?

Can anyone help me?

Thanks!
 

crigri said:
But is this really a problem?
Click to expand...
Yes, a planarity pb. and - by this - a yield problem. The foundry won't let you ignore such violations. Anyway, should be easy to fix.
 

Yes, it it is/was a foundary problem. We have some scripts solving this problems by inserting dummy cells.

kind regards
 

Hi everyone,

i have the same problem in my layout work....

the strange thing is that i have no gaps exceeding that 10um limit.... but it keeps surrounding the area (with the error marker in DRC) where i used top metal (Metal 4)... and if i put dummys as specified on rules it starts surrounding them too, i can't find anyway to solve this damn problem.

This error also occurs when i use corners for a pad ring... quite strange considering those are fully tested standard cells.....

Is there anyway to solve this problem automatically? (i heard in a document of AMS it may be a "NO FILL" layer or something like that)?
 

I'd suggest to find in the DRC rules file the corresponding rule (which generates this error marker and message). This should give you a hint if possibly an inhibit layer (a layer which disables the DRC check for special regions like pad ring) is missing. Actually this also should be described in the PDK docu.
 

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