urian
Full Member level 3
hi,there
i am working clock circuit with cmos logic gate,i.e,inverter,nand2,nand3,nor2,and the high level is 1.2v with low level 0v.
i want to set the rise time and fall time of them to a equal value.
so i short the input of them and give a vdc input and run the dc analysis while sweeping the input from 0 to 1.2v.
then i change the W/L of the transistor until i find that the cross point of input and ouput is nearly 0.6v on both of them.
next i test the rise/fall time of them,but only to find that they are not equal.
then i change the W/L again to set the rise/fall time equal,but find that the cross point of input and output is far away from 0.6v.
So,which method should i adopt?
i am working clock circuit with cmos logic gate,i.e,inverter,nand2,nand3,nor2,and the high level is 1.2v with low level 0v.
i want to set the rise time and fall time of them to a equal value.
so i short the input of them and give a vdc input and run the dc analysis while sweeping the input from 0 to 1.2v.
then i change the W/L of the transistor until i find that the cross point of input and ouput is nearly 0.6v on both of them.
next i test the rise/fall time of them,but only to find that they are not equal.
then i change the W/L again to set the rise/fall time equal,but find that the cross point of input and output is far away from 0.6v.
So,which method should i adopt?