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Looking for materials about SDC constraints

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Haven't used these a whole lot... but does anyone else find them a little confusing? i.e the 'naming' of the constraints don't always seem straight forward.

I guess once you understand them it's Ok, but initially they don't always seem intuitive..

Any good references for SDC? i.e a tutorial that might point out some of these 'gotchas' and caveats?
 

Re: SDC constraints

I too, would like to get this information. I've been looking for days. I've found some good resources that explain design constraining, but nothing that offers fully constrained design examples.

Specifically I would like to see how someone would constrain input and output I/O's using the fpga-centric timing analysis, requiring virtual clocks.

Thanks
 

Re: SDC constraints

Try this site. There is all kinds of information on how to write SDC files, tutorials and etc....

**broken link removed**
 

Re: SDC constraints

Tried the link but it was invalid. Anyone else have this pdf document?
 

Hi,
Maybe you should try going through the Design Compiler userguide "Defining Design Constraints" topic...It will give you a better understanding of SDC.
But to comprehend all those concepts you need patience to read and experiment the things in there.

You can get design compiler ug in the forum..just search for it
 
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