near procedure :syntax error - error message

Hi all,
The following code snippet when compiled


procedure ApplyReset (signal i_clk: in std_logic
signal i_reset: out std_logic) is
begin
wait until i_clk = '1' ; i_reset <= '1';
wait until i_clk = '1'; i_reset <='0';
end ApplyReset;


The following error message is shown;
near procedure :syntax error

i appreciate your help and time

thanks
lok

Re: procedure error

Hi,

The semicolon is missing between the two procedure parameters:

signal i_clk: in std_logic ; signal i_reset: out std_logic

Devas

Re: procedure error

Hi thanks for your reply. Even in this case also giving the same error.
Infact I am giving my complete testbench herewith. Please help me. It is giving lot of syntax error.
You people could run it by removing instantiated component and port mapping.

Please help me. It is eating all my time
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

--parameter declaration;
constant WL : integer:= 8;
constant IR : integer:= 4;
constant IC : integer:= 5;
constant THRESHOLD : integer:= 0;

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT harris_corner_top
generic( WL : integer:= 8;
IR : integer:= 5;
IC : integer:= 5;
THRESHOLD : integer:= 5
);
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_R : IN std_logic_vector(12 downto 0);
i_C : IN std_logic_vector(12 downto 0);
i_start_image : IN std_logic;
i_end_image : IN std_logic;
i_data_valid : IN std_logic;
i_pixel_data : IN std_logic_vector(7 downto 0);
o_data_valid : OUT std_logic;
o_corner_data : OUT std_logic;
o_start_image : OUT std_logic;
o_end_image : OUT std_logic
);
END COMPONENT;


--Inputs
signal i_clk : std_logic := '0';
signal i_reset : std_logic := '0';
signal i_R : std_logic_vector(12 downto 0) := (others => '0');
signal i_C : std_logic_vector(12 downto 0) := (others => '0');
signal i_start_image : std_logic := '0';
signal i_end_image : std_logic := '0';
signal i_data_valid : std_logic := '0';
signal i_pixel_data : std_logic_vector(7 downto 0) := (others => '0');

--Outputs
signal o_data_valid : std_logic;
signal o_corner_data : std_logic;
signal o_start_image : std_logic;
signal o_end_image : std_logic;

-- Clock period definitions
constant i_clk_period : time := 1us;

-- internal signal declaration....
type memory_0 is array (0 to IR*IC-1) of integer;
type memory_1 is array (0 to 8) of real;
type memory_2 is array (0 to IR*IC-1) of real;

signal pixelImage: memory_0;
signal dx, dy, gaussian: memory_1;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: harris_corner_top
generic map(WL=>8, IR=>5, IC=>5, THRESHOLD=>0)
PORT MAP (
i_clk => i_clk,
i_reset => i_reset,
i_R => i_R,
i_C => i_C,
i_start_image => i_start_image,
i_end_image => i_end_image,
i_data_valid => i_data_valid,
i_pixel_data => i_pixel_data,
o_data_valid => o_data_valid,
o_corner_data => o_corner_data,
o_start_image => o_start_image,
o_end_image => o_end_image
);

-- Clock process definitions
i_clk_process rocess
begin
i_clk <= '0';
wait for i_clk_period/2;
i_clk <= '1';
wait for i_clk_period/2;
end process;


procedure ApplyReset (signal clk : in std_logic;
signal reset: out std_logic) is
begin
wait until falling_edge(clk) ; -- reset <= '1';
wait until falling_edge(clk); --reset <= '0';
end ApplyReset;

procedure PrepareInput is
begin
dx(0) <= -1; dy(0) <= -1;
dx(1) <= 0; dy(1) <= -1;
dx(2) <= 1; dy(2) <= -1;
dx(3) <= -1; dy(3) <= 0;
dx(4) <= 0; dy(4) <= 0;
dx(5) <= 1; dy(5) <= 0;
dx(6) <= -1; dy(6) <= 1;
dx(7) <= 0; dy(7) <= 1;
dx(8) <= 1; dy(8) <= 1;

-- Sigma = 1.4 ---g33
gaussian(0) <= 0.0924; gaussian(1) <= 0.1192; gaussian(2) <= 0.0924;
gaussian(3) <= 0.1192; gaussian(4) <= 0.1538; gaussian(5) <= 0.1192;
gaussian(6) <= 0.0924; gaussian(7) <= 0.1192; gaussian(8) <= 0.0924;

-- file file_in : text open read_mode is "data/input/lena_64_64.txt";
--file_open(file_in, "data/input/lena_64_64.txt", read_mode);

for(i=0;i<IR;i=i+1) loop
for(j=0;j<IC; j=j+1) loop
pixelImage(i*IC+j) = buf_in;
end loop;
end loop;
end PrepareInput;


procedure convolution_task()
variable d, rowTotal, colTotal, center, conv_address : integer;
begin
center := 1;
conv_address := 0;
for row in 0 to IR loop
for col in 0 to IC loop
d <= 0;
for rowOffset in -center to center loop
for colOffset in -center to center loop
rowTotal := row + rowOffset;
colTotal := col+colOffset;
if(rowTotal < 0 or rowTotal > IR-1 or colTotal < 0 or colTotal > IC-1) then
p(d) <= 0;
else
p(d) <= conv_in(rowTotal*IC+colTotal);
end if;
d <= d+1;
end loop;
end loop;

conv_out(conv_address) = p(0) * kernel(8) + p(1) * kernel(7) + p(2) * kernel(6) +
p(3) * kernel(5) + p(4) * kernel(4) + p(5) * kernel(3) +
p(6) * kernel(2) + p(7) * kernel(1) + p(8) * kernel(0) ;

conv_address := conv_address +1;
end loop;
end loop;
end procedure;



procedure find_mult()
begin
for i in 0 to IR loop
for j in 0 to IC loop
ix2(i*IC+j) = ix(i*IC+j) * ix(i*IC+j);
iy2(i*IC+j) = iy(i*IC+j) * iy(i*IC+j);
ixiy(i*IC+j)= ix(i*IC+j) * iy(i*IC+j);
end loop;
end loop;
end procedure;


procedure find_cornernessmap();
begin
for i in 0 to IR loop
for j in 0 to IC loop
corn = ((A_matrix(i*IC+j) * B_matrix(i*IC+j)) - (C_matrix(i*IC+j) * C_matrix(i*IC+j)))- (0.05 * (A_matrix(i*IC+j)+B_matrix(i*IC+j))* (A_matrix(i*IC+j)+B_matrix(i*IC+j)));

cornerness(i*IC+j) <= corn;
end loop;
end loop;
end procedure;



procedure non_maximal_sppression();
integer d, rowTotal, colTotal, count, center=1;
begin
for row in 0 to IR loop
for col in 0 to IC loop
d <= 0;
for rowOffset in -center to center loop
for colOffset in -center to center loop
rowTotal <= row+rowOffset;
colTotal <= col+colOffset;
if(rowTotal < 0 or rowTotal > IR-1 or colTotal < 0 or colTotal > IC-1) then
non(d) <= 0;
else
non(d) <= cornerness(rowTotal*IC+colTotal);
d <= d+1;
end loop;
end loop;

count <= 0;
for i in 0 to 3 loop
for j in 0 to 3 loop
if(cornerness(row*IC+col) < non(i*3+j)) then
count <= 1;
end if;
end loop;
end loop;

if(count = '0') then
non_max(row*IC+col) <= cornerness(row*IC+col);
else
non_max(row*IC+col) <= 0;
end if;

end loop;
end loop;
end procedure;


procedure Thresholding;
begin
for i in 0 to IR loop
for j in 0 to IC loop
if(non_max(i*IC+j) > THRESHOLD) then
thresh[i*IC+j] = 1;
else
thresh[i*IC+j] =0;
end if;
end loop;
end loop;
end procedure;

procedure ready_ix is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= pixelImage(i*IC+j);
end loop;
end loop;

for i in 0 to K_SIZE loop
for j in 0 to K_SIZE loop
kernel(i*K_SIZE+j) <= dx(i*K_SIZE+j);
end loop;
end loop;
end ready_ix;

procedure copy_ix is
begin
for i in 0 to IR loop
for j in 0 to IC loop
ix(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end procedure;

procedure ready_iy is
begin
for i in 0 to K_SIZE loop
for j in 0 to K_SIZE loop
kernel(i*K_SIZE+j) <= dy(i*K_SIZE+j);
end loop;
end loop;
end ready_iy;

procedure copy_iy is
begin
for i in 0 to IR loop
for j in 0 to IC loop
iy(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_iy;

procedure ready_a is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= ix2(i*IC+j);
end loop;
end loop;

for i in 0 to K_SIZE loop
for j in 0 to K_SIZE loop
kernel(i*K_SIZE+j) <= gaussian(i*K_SIZE+j);
end loop;
end loop;
end ready_a;

procedure copy_a is
begin
for i in 0 to IR loop
for j in 0 to IC loop
a(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_a;

procedure ready_b is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= iy2(i*IC+j);
end loop;
end loop;
end ready_b;

procedure copy_b is
begin
for i in 0 to IR loop
for j in 0 to IC loop
b(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_b;

procedure ready_c is
begin
for i in 0 to IR loop
for j in 0 to IC loop
conv_in(i*IC+j) <= iy2(i*IC+j);
end loop;
end loop;
end ready_c;

procedure copy_c is
begin
for i in 0 to IR loop
for j in 0 to IC loop
b(i*IC+j) <= conv_out(i*IC+j);
end loop;
end loop;
end copy_c;



-- Stimulus process
stim_proc: process
begin
-- Wait 100 ns for global reset to finish
-- #500;

-- Apply Reset
ApplyReset(i_clk, i_reset);
report"ApplyReset is done\n";

-- #300;

PrepareInput();
report"PrepareInput is done\n";

erady_ix();
convolution_task();
copy_ix();
report"Ix computation is done\n";

erady_iy();
convolution_task();
copy_iy();
report"Iy computation is done\n";

find_mult();
report"Multiplication of differentiation is done\n";

ready_a();
convolution_task();
copy_a();
report"A computation is done\n";

ready_b();
convolution_task();
copy_b();
report"B computation is done\n";

ready_c();
convolution_task();
copy_c();
report"C_matrix computation is done\n";

find_cornernessmap();
report"Cornerness map is done\n";

non_maximal_sppression();
report"Non-maximum suppression is done\n";

Thresholding();
report"Thresholding is done\n";

PrepareInput_RTL();
report"PrepareInputRTL is done\n";

wait;
end process;

END;

Re: procedure error

Hi,

You have to declare your procedures in the declaration part of the architecture or process:

architecture rtl of entity is

<declaration part>

begin

end


process

<declaration part>

begin

end

Devas

procedure error

HI Devas,

ThankQ a lot yaar. I am new to VHDL.