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Area per Logic element in FPGA???

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pinkyvidya

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Can anyone please tell me how to represent logic elements in terms of area.
In Quartus utilization factor is represented in terms of logic elements. I need to know area per logic element in its respective units.Please help.Thanks in advance
 

we can give area constraint in constraint file like xNyM to xPyQ bound for particular module... this way we can bound area for particular logic
 

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