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Converting boolean formula into verilog and vhdl code

Thread starter gtan
Start date Jan 5, 2010

Status: Not open for further replies.

Jan 5, 2010

#1

G

gtan

Newbie level 3

Could someone convert the boolean formula AB'+C into verilog and vhdl code for me?
Thnks.

Jan 5, 2010

#2

S

svhb

Full Member level 5

I think you need some basic introduction course/book/webpage.

https://www.asic-world.com/verilog/verilog_one_day.html

Status: Not open for further replies.

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