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on: design FIFO for packet based data flow

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ydao

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requirement : no packet corruption occurs

any one could share some experience on this topic?
or
any useful link on it?

thanks in advance.

ps. maybe we could discuss more technology here :)
 

Could you be more specific with what you're looking for? What kind of corruption are you talking about?

A lot times you if you give a little bit of info about your application, it helps people to understand what problem it is you're trying to solve.

Cheers,
Radix
 

I guess that you have to develop Async FIFO. There are a lot of information about implementation of Async FIFO in FPGA. If FIFO size is not enough. You may consider such kind of architecture

Input -> FIFO1 -> Mem Controller (SRAM/SDRAM) -> FIFO2 -> Output

Note: Caculate the bandwidth of each path to garantee the throughput of Output
 

You must consider following point:
(1) synchronous ro asynchronous
(2) the threshold for writing and reading.
(3) the error packet filtering.
(4) the maxium packet length you support.

for FIFO design,you can reference www.xilinx.com.

I hope this can help you,good luck.
 

Thanks for your kind.
In fact, I'm using the architecure as same as that elektrom give out. And what wufendbo point out is very important for the design. I feel it is so difficult to prevent the output packets from being corrupted after such complex process as well as keep the throughput as good as possible.
thank you anyway!
 

I designed a general packet fifo for using in my designs. It's a fix length packet. It has two level countr for read and write operation. It had to control externally in both read and write opration.
 

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