oak_tree
Newbie level 5
Our next chip is going to be in 65 nm. That's a big jump from 180 nm. I'm not too familar with the flow, and I'll appreciate any input.
My first question is in the RTL level. I know that UPF/CPF is used to assign a voltage and power mode to each module. What if an exixting module contains some logic that is in the 'always-on' domain and other parts that are going to be off (PSO). I assume that I need to create 2 different modules (i.e., rewriting the RTL) so I can assign a power mode to each portion. Do I have to rewrite the RTL and create 2 modules or is there an easier way (like in VHDL, using 'block' statement within the code. The synthesis creates a different module for the block)?
My first question is in the RTL level. I know that UPF/CPF is used to assign a voltage and power mode to each module. What if an exixting module contains some logic that is in the 'always-on' domain and other parts that are going to be off (PSO). I assume that I need to create 2 different modules (i.e., rewriting the RTL) so I can assign a power mode to each portion. Do I have to rewrite the RTL and create 2 modules or is there an easier way (like in VHDL, using 'block' statement within the code. The synthesis creates a different module for the block)?