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Multi voltage and multi power mode design partitioning

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oak_tree

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Our next chip is going to be in 65 nm. That's a big jump from 180 nm. I'm not too familar with the flow, and I'll appreciate any input.

My first question is in the RTL level. I know that UPF/CPF is used to assign a voltage and power mode to each module. What if an exixting module contains some logic that is in the 'always-on' domain and other parts that are going to be off (PSO). I assume that I need to create 2 different modules (i.e., rewriting the RTL) so I can assign a power mode to each portion. Do I have to rewrite the RTL and create 2 modules or is there an easier way (like in VHDL, using 'block' statement within the code. The synthesis creates a different module for the block)?
 

rsqf

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oak_tree said:
Our next chip is going to be in 65 nm. That's a big jump from 180 nm. I'm not too familar with the flow, and I'll appreciate any input.

My first question is in the RTL level. I know that UPF/CPF is used to assign a voltage and power mode to each module. What if an exixting module contains some logic that is in the 'always-on' domain and other parts that are going to be off (PSO). I assume that I need to create 2 different modules (i.e., rewriting the RTL) so I can assign a power mode to each portion. Do I have to rewrite the RTL and create 2 modules or is there an easier way (like in VHDL, using 'block' statement within the code. The synthesis creates a different module for the block)?

And I have a question : Do you want to create two seperated power domain, and there is a module named "A", in one power domain, and another module named "B" which is the same as module A, in the other domain? If the description is correct, I think you need not to rewrite the RTL code.
 

oak_tree

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Thanks for the answer.

What I meant is that I have currently one module ('A'). Let's say that I have a state machine that I'd like to put on 'always-on' power domain, and I'd like to shut off the power to the rest of the logic in that module. Do I have to create a new module ('B'. Module B is instantiated in module 'A') for the FSM, and leave the rest of the logic in module 'A' or there is an easier way to separate the logic in module 'A'?
 

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