On resistance of diode and mosfet

Hello all,

Can anybody susgest how to calculate on resistance of diode and mosfet...
AFAIK, on resistance and breakdown voltage of diode is more than that of mosfet for the given area...... is it correct???......
what is the reason behind??


Deepak.

deepak242003 said:

... on resistance and breakdown voltage of diode is more than that of mosfet for the given area...... is it correct???......
what is the reason behind??

Click to expand...

On resistance: Vds of a mosfet can be much lower than Vforward of a junction diode.
Breakdown voltage: BV of a mosfet can never be higher than the parasitic diodes associated with it.

The "area" consumed by a lateral MOSFET is way, way larger
than the feature cross-sectional area that supports conduction.
In a vertical diode the two are designed to be as close as
possible. An integrated, quasi-vertical or substrate vertical
diode still come closer than the FET. Even vertical power
MOSFETs have a fairly high "overhead" (source area
>> channel, neck region cross-section).

For the MOSFET it is very straight forward. The datasheet should specify the on resistance per area for a certain gate source voltage and temperature.

If your gate source voltage is lower or the temperature is different then you should simulate it.

1. Be careful with very large devices. The interconnect metal starts to become more dominant and you will need to make a detailed simulation of the metalization to accurately calculate on resistance.
2. With some power dissipation be sure to calculate the self heating.

For the diode sometimes a forward resistance is specified for a particular forward drop. You should simulate it. I don't know what process you use but most CMOS processes have only a limited number of "free" diodes. If you use a Schottky then be careful to size the device so the forward drop is lower than the vbe required for the parastic pnp to turn on.

Thanks to alll for their replies......

What I mean to ask is if the area is restricted in ESD.. say 500um2.... then should I prefer diode connected MOS or pn diode..??.

I suppose diode has more on resistance and breakdown voltage than gate connected mos.. is it correct??
Is there any other paramters to be considered..??
btw we are considering umc65 process ..

Deepak.

use a PN diode for ESD. diodes can allow really large currents if the voltage drop is too large.

https://org.ntnu.no/solarcells/pics/diode.jpg

This is what you want for a good ESD device.

eecs4ever said:

This is what you want for a good ESD device.

Click to expand...

Sure: the avalanche breakdown is steep and seems nice for ESD protection. But how would you adjust an appropriate avalanche breakdown voltage within a std. CMOS process?

erikl said:

eecs4ever said:

This is what you want for a good ESD device.

Click to expand...

Sure: the avalanche breakdown is steep and seems nice for ESD protection. But how would you adjust an appropriate avalanche breakdown voltage within a std. CMOS process?

Click to expand...

Yes, you can't adjust this value. But it seems to me that deepak is asking about the on-resistance in the forward biased regions since he is asking about diode connected mosfet vs a PN diode. I've never seen a diode connected mosfet thats designed to be operated in the reverse break down case.

Dear eecs4ever and erik.
thanks for ur replies...

If the diode has large on resistance, ur desing window wil decrease, as ur snapback voltage has to be less than this voltage..... so I was wondering if we can use diode connected mosfet(low on resistance,low voltage drop--> more design window..)..

let me know ur views on this....

deepak

eecs4ever said:

... it seems to me that deepak is asking about the on-resistance in the forward biased regions since he is asking about diode connected mosfet vs a PN diode.

Click to expand...

In such case it's necessary to stack several diodes on each other, e.g. use a stack of 6 or 7 diodes to protect against an overvoltage of, say, >5V. Each of these diodes (apart perhaps from the last one, if the protection circuit sucks to GND) must have their own n-well, of course. These diodes own a significant series resistance.
I've tried such a protection scheme against a potentially possible high overvoltage on a gate input of an opAmp. For a max. possible current of 1mA it needed a stack of 6 p+on-nwell 100*100(µm)² diodes to limit their added forward voltages to 5V. This is a total area consumption equivalent to about 3 .. 4 pads. Not quite cheap!

deepak242003 said:

... so I was wondering if we can use diode connected mosfet

Click to expand...

For the same purpose I also tried a stack of 6 diode connected mosfets (all in their separate n-well) : for the same protection outcome (5V @ 1mA) this needed only about 1/5 of the area of the p+n diodes protection stack. Still a lot, but definitely the cheaper solution!

eecs4ever said:

I've never seen a diode connected mosfet thats designed to be operated in the reverse break down case.

Click to expand...

Of course not: the reverse operation would just activate the parasitic bulk junction diode in forward direction.