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Flase_Path reports in DC/PT

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koppolu1981

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Hi All,
I have done Asic-synthesis of mys using DC and STA using PT. I have specified all paths between clock-domians as fasle paths.
For my Gatelevel simulation with SDF back-annotation I'm seeing violations on signals crossing the clock domains.

If I get the complete false_path for my design, I can disable all the clock crossing violations in GLS.

Can anybody tell me how to get the report of all false paths in either DC/PT?

Thanks in Advance,
Ram
 

I don't think you can get DC or PT to tell you all the false paths in your design. There are other design analysis and clock domain crossing tools that might provide some guidance on which paths in your design might be false or multi-cycle. But ultimately it's up to the designer to determine which paths are subject to valid timing analysis.
 

did u know abt SPYGLASS.

Just try to read if SPYGLASS can do this

BR

SING
 

I don't expect DC/PT to find the false paths for my design.
My query is if I specify the false paths for the synthesis in my constraints, can I use the DC to report paths in the netlist, that are specified as false paths in the constraints input file to DC?
 

if you want to get all cross-domain path, you can use spyglass!
 

You can load the design in PT, apply the set_false_path to every timing path you want constrained as false and then do a "report_exceptions -ignored" command.
 

There may be a different approach. Assuming your design has a synchronizer circuit for handling your clock domain crossing, you should be able to disable the timing setup/hold check (or zero it out) for the first flop of the synchronizer. This should stop the verification tool from propagating X's when it fails the timing check.
 

Handling the cross async. clock domain's gate-level sim, I usually modify the sdf file's timing check part to avoid the "X" in simulation.
 

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