aibrahim
Junior Member level 2
excess loop delay
Dear All,
i am modeling a CT delta sigma modulator using simulink , now i am trying to model excess loop delay .
I try two methods:
1. use a transport delay but it the delay appears as an increase in the rise time not a delay in the output signal of this block.
2. a D-ff clocked with a delayed clock but really output delay exceed what i expect.
I guess it's a simulatin time settings problem, so i try a variable step method and define min step with a value lower than my delay vaue.
but still i have the sam problem
anyone can help me or suggest another method to model excess loop delay.
Advanced thanks
Dear All,
i am modeling a CT delta sigma modulator using simulink , now i am trying to model excess loop delay .
I try two methods:
1. use a transport delay but it the delay appears as an increase in the rise time not a delay in the output signal of this block.
2. a D-ff clocked with a delayed clock but really output delay exceed what i expect.
I guess it's a simulatin time settings problem, so i try a variable step method and define min step with a value lower than my delay vaue.
but still i have the sam problem
anyone can help me or suggest another method to model excess loop delay.
Advanced thanks
