resistor and cap matching of hybrid dac for sar adc

hybrid dac

I am working on a 10-bit sar adc that uses cap and resistor ladder. 8 msb for the resistor ladder and 2 lsb for cap array. The spec is 0.5lsb dnl, don't care about snr...

What are the matching requirements for the resistor and cap and how to analyze them?

Can anyone help?

hybrid cap issues

0.5*2^-8 ≈ 0.2% for the resistor ladder
and
0.5*2^-10 ≈ 0.05% for the cap array.
Analyze/simulate the postLayout (extracted) netlist.

resistor array pattern of dac

Thanks for your reply.

The matching of resistor is 0.5 lsb of 8 bit and the matching of cap is 0.5 lsb of 10 bit .

But I still have question, the matching of cap is 0.5lsb of 10bit or 2 bit ?

dac resistor 10 bit

cxm12 said:

Thanks for your reply.

The matching of resistor is 0.5 lsb of 8 bit and the matching of cap is 0.5 lsb of 10 bit .

But I still have question, the matching of cap is 0.5lsb of 10bit or 2 bit ?

Click to expand...

Matching of cap is 0.5lsb of 10bit, as you correctly stated above ;-)

sar hybrid adc

erikl said:

0.5*2^-8 ≈ 0.2% for the resistor ladder
and
0.5*2^-10 ≈ 0.05% for the cap array.
Analyze/simulate the postLayout (extracted) netlist.

Click to expand...

The problem is that most of the "standard" parasitic extraction tools do not guarantee extraction accuracy, they can be easily off by 15-20%. The error can be as high as 100-400% for incorrect extraction setup.

As a result, capacitance weighting can be significantly off the ideal (1/2/4/8/16/...).

We have seen our clients' chips failing (under-performing) due to ADC issues related to incorrect capacitance weighting, and parasitic extraction tools were not capturing that effect.

Max

ic dac 12-bit 1/2 lsb hyb

timof said:

The problem is that most of the "standard" parasitic extraction tools do not guarantee extraction accuracy, they can be easily off by 15-20%. The error can be as high as 100-400% for incorrect extraction setup.

Max

Click to expand...

Never heard of that. Re. incorrect extraction setup: The fab/foundry is responsible of supplying an accurate extraction rules file; the extraction tools can of course provide the necessary accuracy.

For a mature process - i.e. after quite a few parameter extractions - our extraction rules are accurate enough even for converters with a (1 of) 12-bit resolution (i.e. ≤ 250ppm inaccuracy). This has been proven for several ADCs/DACs.

ErikL

capacitor matching and resister matching

erikl said:

Never heard of that. Re. incorrect extraction setup: The fab/foundry is responsible of supplying an accurate extraction rules file; the extraction tools can of course provide the necessary accuracy.

Click to expand...

Yes, they are responsible, but very often extraction rules, models, PDKs etc. are not accurate enough - that's why many fabless companies generate their own test patterns and measure them to guarantee the accuracy.

Some of the analog blocks require to resolve accuracy of coupling capacitance of the order of 0.1-0.5% of the total net capacitance - pattern matching tools (most of the "standard" parasitic extraction tools) do not provide that accuracy.

erikl said:

For a mature process - i.e. after quite a few parameter extractions - our extraction rules are accurate enough even for converters with a (1 of) 12-bit resolution (i.e. ≤ 250ppm inaccuracy). This has been proven for several ADCs/DACs.

Click to expand...

Are you changing your extraction rules after each parasitic extraction?

Very often people rely (blindly) on parasitic extractors, without knowing the limitations and accuracy issues. Of course, a user with good knowledge of these limitations can find workarounds and get good results even with imperfect tools.

Max

12 bit sar adc

timof said:

Are you changing your extraction rules after each parasitic extraction?
Max

Click to expand...

Of course not . But about 3..4 times a year - at least after every important process change - extractions from test structures are repeated, and the models and extraction rules being updated. Hence for a, e.g. 0.18µm process already running for about 5 years (mature process), we've had around 15 updates, and thus the models and extraction rules are rather exact, so one can trust even a 0.05% resolution for the parasitics. This is not true, of course, for a new process.

dac r2r ladder matching

erikl said:

Of course not . But about 3..4 times a year - at least after every important process change - extractions from test structures are repeated, and the models and extraction rules being updated. Hence for a, e.g. 0.18µm process already running for about 5 years (mature process), we've had around 15 updates, and thus the models and extraction rules are rather exact, so one can trust even a 0.05% resolution for the parasitics. This is not true, of course, for a new process.

Click to expand...

From what you describe it appears that your company has a smart, knowledgeable CAD/parasitic extraction group - this is very rare. I guess that whenever they see a big difference between parasitic extraction and measurements, they would add this pattern into a set of patterns that are simulated by a field solver and written into a database. This would work, unless you care for such things as time to run experimental lots, cost, measurements/analysis, etc.

But not every company can afford that (neither from resources/manpower viewpoint, nor from time to market or experimental lot expense viewpoint).

By the way, with mesh-based field solvers (like Raphael etc.), it is extremely difficult to get an accuracy better than 0.5-1% - due to mesh effect, boundary conditions effect, etc.

There are extraction tools, however, that would give you the desired accuracy (say, 0.1%) form the first run.

resistor capacitor hybrid adc

timof said:

From what you describe it appears that your company has a smart, knowledgeable CAD/parasitic extraction group - this is very rare. I guess that whenever they see a big difference between parasitic extraction and measurements, they would add this pattern into a set of patterns that are simulated by a field solver and written into a database. This would work, unless you care for such things as time to run experimental lots, cost, measurements/analysis, etc.

But not every company can afford that (neither from resources/manpower viewpoint, nor from time to market or experimental lot expense viewpoint).

Click to expand...

You're right, we've got such an extraction & modelling crew. Of course it's expensive, but mixed analog reruns also cost a lot.

timof said:

There are extraction tools, however, that would give you the desired accuracy (say, 0.1%) form the first run.

Click to expand...

Even better. How else could you succeed on a 12-bit converter - with a standard CMOS process - on the 1st (or may be 2nd ;-) ) run?

sar adc hybrid

There is one more very important point - the value of the unit capacitor (and area it occupies). The larger the unit capacitor value, the less important is the parasitic capacitance (and, accordingly, parasitic extraction accuracy). The price you pay for correct weighting is chip area and cost.

There are many more details (the devil is in the details) when we discuss extraction accuracy - for example, is this accuracy referred to parasitic capacitance, or to (parasitic+useful capacitance)? The difference between these two can be huge.

Also, as far as I know, "standard" parasitic extractors have big problems in "blocking" (i.e. ignoring) device related capacitances (that are taken into account in Spice/compact models of devices - MOM/MIM capacitors, transistors, etc.), and leaving only parasitic capacitances between devices and surrounding nets.

My main point remains the same - parasitic extraction is not a trivial, automatic procedure, and requires either a very reliable extraction tool, or deep expertise plus trial and error time. Extraction (without multiple empirical trial runs and corrections) with accuracy better than ~+/-10% is very nontrivial, and anything better than 1% is an extremely difficult task.