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how to use wait statement for memory in verilog

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Mkanimozhi

Mkanimozhi

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verilog wait

hi to every one
here in the below mentioned code i am getting error on wait sout,

sout is my memory , how to use the meory in wait statement in verilog, i am not getting any error in vhdl.tell me the solution soon.

reg [5:0] sout [2:0];

always
begin
wait sout
for (y=1;y<=nby2by3;y=y+1)
temp[y] =sout[y];
end

regards
kanimozhi
 

wait verilog

Mkanimozhi said:
hi to every one
here in the below mentioned code i am getting error on wait sout,

sout is my memory , how to use the meory in wait statement in verilog, i am not getting any error in vhdl.tell me the solution soon.

reg [5:0] sout [2:0];

always
begin
wait sout
for (y=1;y<=nby2by3;y=y+1)
temp[y] =sout[y];
end

regards
kanimozhi
Click to expand...

Is this for Synthesis or simulation alone? If it sim alone, try:

Code: 
always @(sout)
begin
 
 for (y=1;y<=nby2by3;y=y+1)
   temp[y] =sout[y];
end

Or even better (if you have SystemVerilog aware tools)

Code: 
always_comb
begin
 for (y=1;y<=nby2by3;y=y+1)
   temp[y] =sout[y];
end

HTH
Ajeetha, CVC
Next SV course starting in Feb 09 end. See:
https://sv-verif.blogspot.com for details
 

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