help in vhdl code.... no signal is generating

help in vhdl code.......

hai friends
i have pci9054 device i want to generate write ,chip select signals from it i wrote avhdl code for that .It doesn't giving any error wen compiling but no signal is generating can any one can correct my code .I want to generate write and chip select signals for specified clock edges and for some predefined duration plz help. i am adding my vhdl code here
thanks


-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation

---------------------------------------------
--Module : PCI9054 interface Module
--File : PCI9054_IF.vhd
--Library : IEEE;
--Description : PCI9054 interface controller
--Simulator : MAX+plus II /WindowsXP
--Synthesizer :
--Author : jerins
--Created : 04/12/2008
--Last update : 05/12/2008
---------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------

entity PCI9054_IF is
port(
CLK : in std_logic;
LHOLD : in std_logic;
ADS_N : in std_logic;
LA : in std_logic_vector (1 downto 0);
LHOLDA : out std_logic;
WR_n : out std_logic;
CS : out std_logic;
CNT : inout INTEGER RANGE 0 TO 5
);
end ;

architecture RTL of PCI9054_IF is
type COUNT_TYPE is (TRUE,FALSE);
signal COUNT : COUNT_TYPE;


begin

--Grant for local bus request
X1 : process(CLK)
begin
if (CLK'event and CLK = '1') then
if LHOLD = '1' then
LHOLDA <= LHOLD;
else
LHOLDA <= '0';
end if;
end if;
end process X1;

--Clock counter

X2 : process(CLK)
begin
if ( ADS_N ='0') then
if(LA = "11") then
COUNT <= TRUE;
else
COUNT <= FALSE;
end if;
end if ;
if (COUNT = TRUE )then
CNT <= CNT + 1;
end if;
end process X2;

--signal generation


X3 : process (CLK)
begin
if (COUNT = TRUE) then
case CNT is

when 1 =>
CS <= '0';
when 3 =>
WR_n <= '0';
when others =>
CS <= '1';
WR_n <= '1';
end case;
end if;
end process X3;
end RTL ;

Re: help in vhdl code.......

2 : process(CLK) ---sensitive but you donot use it in your process.
begin
if ( ADS_N ='0') then
if(LA = "11") then
COUNT <= TRUE;
else
COUNT <= FALSE;
end if;
end if ;
if (COUNT = TRUE )then
CNT <= CNT + 1;
end if;
end process X2;

--signal generation


X3 : process (CLK) ---sensitive but you donot use it in your process.
begin
if (COUNT = TRUE) then
case CNT is

when 1 =>
CS <= '0';
when 3 =>
WR_n <= '0';
when others =>
CS <= '1';
WR_n <= '1';
end case;
end if;
end process X3;
end RTL ;