dadda007
Newbie level 5
related:www.edn.com/article/ca47273.html
I have written a code to take in serial data from a RS-232 link and store it in a register. I intend to generate 2 signals , one signal ack1 which goes high after a valid start bit has been obtained and another signal ack2 after all the 8 data bits have been received correctly. To check the validity i have used an oversampling clock which samples each bit duration at 16 times the baud rate clock and uses maximal logic for evaluating the same. However after simulation i was getting no value into the register and also faulty value for ack1 and ack2 ....please help !!!!!
I have written a code to take in serial data from a RS-232 link and store it in a register. I intend to generate 2 signals , one signal ack1 which goes high after a valid start bit has been obtained and another signal ack2 after all the 8 data bits have been received correctly. To check the validity i have used an oversampling clock which samples each bit duration at 16 times the baud rate clock and uses maximal logic for evaluating the same. However after simulation i was getting no value into the register and also faulty value for ack1 and ack2 ....please help !!!!!
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity rs232_lport is
port (
data : in BIT;
clk_rs232 : inout STD_LOGIC;
baudrate : in STD_LOGIC;
-- lport_clk : out BIT:='0';
ack1 : out BIT;
ack2 : out BIT;
-- check : out BIT;
-- lport_data : out BIT_VECTOR(3 downto 0);
input_reg : buffer BIT_VECTOR(7 downto 0):="00000000");
end entity;
architecture rs232_lport_behav of rs232_lport is
shared variable med,med1 : BIT_VECTOR(4 downto 0);
shared variable i,lcount_16,dcount,nos_0,nos_1 : integer;
shared variable big,big1,dbit : bit;
shared variable first_4,last_4 : BIT_VECTOR(3 downto 0);
type state_rs232 is (s0,s1,s2);
type state_lport is (idle,f4,l4);
signal l_state : state_lport;
signal rs_state : state_rs232; --Initial state is s0.
begin
process(data)
begin
case rs_state is
when s0=> -- Idle state of state machine
if(data='1') then -- If data is one then set all parameters to zero.
ack1<='0';
rs_state<=s0; -- Back to idle state .....
else
rs_state<=s1; -- If data line is zero then go to state s1.
end if;
when s1=> -- Checks the validity of start bit.
-- check<='1';
for lcount_16 in 1 to 16 loop -- checks the value of the first start bit.
ack2<='0';
ack1<='0';
if (clk_rs232'event )and (clk_rs232='1') and (clk_rs232'last_value='0')then
if(lcount_16=7) then
med(0):=data;
end if;
if(lcount_16=8) then
med(1):=data;
end if;
if(lcount_16=9) then
med(2):=data;
end if;
if(lcount_16=10) then
med(3):=data;
end if;
if(lcount_16=11) then
med(4):=data;
end if;
end if;
end loop;
for i in 0 to 4 loop -- checks the value of start bit using maximal logic.
if(med(i)='0') then
nos_0:=nos_0+1;
end if;
end loop;
for i in 0 to 4 loop
if(med(i)='1') then
nos_1:=nos_1+1;
end if;
end loop;
if(nos_1>nos_0) then
big:='1';
else
big:='0';
end if;
if(big='0') then -- If the value of the start bit is zero then set the value of the ack1 bit to one .....
ack1<='1';
rs_state<=s2; -- Go to state s2
else
ack1<='0';
rs_state<=s0; -- If start bit is 1 goto idle state.
end if;
when s2=> -- This state takes in the value into the register and keeps shifting it.
-- if(ack1='1') then
for dcount in 0 to 7 loop
if(baudrate'event and baudrate='1') then
dbit:=data;
input_reg<='0'&input_reg(7 downto 1);
input_reg(7)<=dbit;
end if;
end loop;
ack2<='1'; -- After all the 8 bits have been shifted set the value of ack2 bit high.
rs_state<=s0; -- Go to state s0 , i.e. the idle state .....
end case;
end process;
end rs232_lport_behav;
