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i can't activate a signal after 12 cycles

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aris12

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hi everybody,
i'm new in vhdl and i'm trying to activate a signal after 12 cycles and then di-activate it again. for example,
start-0-0-0-0-0-0-0-0-0-0-0-0-1-0-end

i have these errors in Modelsim,
error: No feasible emtries for infix operator "+".
error: Type error resolving infix expression "+" as type ieee.std_logic_1164.std_logic_vector.

can anyone tell me what's happening pls and how i can fix it?


Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- =============== Interface Description ===============

entity COUNTER_DEC is

port (clock : in std_logic; -- positive edge
reset : in std_logic;

start : in std_logic; -- start process

done_count: out std_logic -- end of the process

);
end COUNTER_DEC;

architecture COUNTER_DEC_RTL of COUNTER_DEC is


-- =============== Signal Definition ===============

signal tmp : std_logic;
signal active : std_logic;
signal counter: std_logic_vector(3 downto 0);


-- =============== Data Movement ===============

begin

START_COUNTER: process ( clock, reset )

begin

if reset = '1' then
counter <= (others => '0');
tmp <= '0';
active <= '0';

elsif (start = '1' or active = '1') then

if clock'event and clock = '1' then
counter <= (counter + '1');
else
counter <= counter;
tmp <= tmp;
end if;
active <= active xor start;
else
counter <= "0000";
tmp <= '0';
active <= '0';
end if;

if counter = "1100" then
tmp <= '1';
counter <= "0000";
active <= '0';
else
tmp <= '0';
end if;
done_count <= tmp;

end process;

end COUNTER_DEC_RTL;
 

std_logic_vector rol determine definition

The '+' syntax error is easy. You can add numeric values, not bit values. '1' is a bit signal, it can't be added.

You are using numeric_std package, so you have to define your counter as unsigned, not as std_logic_vector.
Unsigned signals can be increased by adding 1.
Code: 
counter <= counter + 1;

But's that only the most obvious problem. I'm rather sure that your counter construct either will be refused by the VHDL compiler or compile but not work as intended. The problem is, you don't define a pure synchronous circuit (with a reset), it's a strange (and most likely unsynthesizable) mixture of synchronous and asynchronous logic.

Basically synchronous logic, that can be synthesized should have a structure like this:

Code: 
IF reset_condition THEN
-- reset code
ELSIF RISING_EDGE(clock_signal) THEN
  -- unconditional synchr. code
  IF condition1 THEN
  -- conditional code
  ELSE
  -- conditional code
  END IF;
END;
I understand well, that some problems don't easily fit this structure. But the issue can't be solved as you tried. The general solution in many FPGA projects is to have a fast system clock and do all processing in this clock domain. An edge of an input signal is e. g. detected synchronously then by comparing a previous and a current state.
 

    A

    aris12

    Points: 2
    Helpful Answer Positive Rating
2 signal counter

FvM thank u very much for the reply.
You are right. i used "unsigned" and the compilation complited sucessfully. the bad is that it doesn't do what i wanted.. :)



Code: 
-- ===========================================================================
-- Project   : COUNTER_DEC 
-- Purpose   : This block after 12 clocks activate output for one pulse. 
-- ===========================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.numeric_std.all;


-- ================ Interface Description ================ 


entity COUNTER_DEC is

  port (clock     : in std_logic;  -- positive edge
        reset     : in std_logic;

        start     : in std_logic;  -- start process
        
        done_count: out std_logic  -- end of the process

        );
end COUNTER_DEC;

architecture COUNTER_DEC_RTL of COUNTER_DEC is


-- ================ Signal Definition ================ 

signal tmp        : std_logic;
signal active1     : std_logic;
signal counter    : std_logic_vector(3 downto 0);
-- signal new_counter: std_logic_vector(3 downto 0);


-- ================ Data Movement ================ 

begin 

START_COUNTER: process ( clock, reset )

begin 

   if reset = '1' then
   
   if reset = '1' then
       counter   <= (others =>  '0');
       tmp       <= '0';
       active1    <= '0';
       
   elsif (start = '1' or active1 = '1') then

   if clock'event and clock = '1' then
          counter <= counter + 1;
   else 
         counter <= counter;
         tmp     <= tmp;
   end if;
   active1  <= active1 or start;
   
   --else
       --  counter <= "0000";
        -- tmp     <= '0';
        -- active1  <= '0';
   end if;
   end if;

   if counter = "0001" then
         tmp     <= '1';
         counter <= "0000";
         active1  <= '0';
   else
         tmp     <= '0';
   end if;
   done_count    <= tmp;
   
end process;

end COUNTER_DEC_RTL;

i also tried to use wait statment. something like this,
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ================= Interface Description ================= 


entity COUNTER_DEC is

  port (clock     : in std_logic;  -- positive edge
        reset     : in std_logic;

        start     : in std_logic;  -- start process
        
        done_count: out std_logic  -- end of the process

        );
end COUNTER_DEC;

architecture COUNTER_DEC_RTL of COUNTER_DEC is

-- ================= Data Movement ================= 

begin 
  
START_COUNTER: process -- ( clock, reset ) 
begin 
  
    if (start = '1') then
    f1: for i in 0 to 12 loop
        wait until (clock'event and clock = '1');
    end loop; 
    done_count    <= '1';
    wait until (clock'event and clock = '0');
    done_count    <= '0';
    end if;

   end process;

end COUNTER_DEC_RTL;

-- The wait statement cannot be used:

  -- 1. In a process with a sensitivity list
  -- 2. In a procedure called from a process with a sensitivity list.
  -- 3. In a function
  -- 4. In a procedure called from a function

What do u think about that? is it ok?
Also, Modelsim accept this code but Quatrus and xilinx ISE didn't.



i don't know why it says that process must contain only one wait statement..
all the books i read says that is ok.
("VHDL Programming by Example - 4th Edition", "VHDL-Cookbook")

propose me pls a good way of doing it.
thanks again
 

determine definition of operator rol

You are using behavioural code, that isn't synthesizable in FPGA. It can be used in simulation ony. The books, you consulted, apparently don't focus on this important difference.

Neither the clock sensitive wait statement in a loop nor the clock sensitive statement for the opposite edge are synthesizable code, unfortunately. (you can use different edges in process or in spearate processes, but not to set the same signal.)

The reason for this restriction is rather simple and understandable to my opinion. FPGA core logic is based on gates and flip-flops. There are smaller differences between FPGA families, but basically, the flip flops have asynchronous (always a reset, sometimes set and synchronous load) and synchronous functions. The synchronous capability is utilizing an edge sensitive clock input, by inverting the clock, it can operate at the othe edge. There's nothing, that would allow to sample a signal on both edges.

Actually your logic is very easy. It can be written straightforward:

Code: 
if reset = '1' then
  counter   <= (others =>  '0');
  done_count <= '0';
elsif rising_edge(clock) then
  if counter >= 12 then
    counter <= "0000";
    done_count <= '1';
  elsif counter > 0  or start = '1' then
    counter <= counter + 1;
    done_count <= '0';
  else
    counter <= "0000";
    done_count <= '0';
  end if;
end if;
 

    A

    aris12

    Points: 2
    Helpful Answer Positive Rating
FvM u r my heroe :) thank u man. it works.
i understood everything u said. thank u. i spend so much time trying to make procedures, functions and many many other things to make it work :)


can u also propose me a good guide for vhdl because i'm trying to use shift operators and i have errors again :)
i use,
ieee.numeric_std.all;
IEEE.NUMERIC_BIT;
and i write for example,
test <= counter rol 1;
where test and counder are "std_logic_vector(3 downto 0);".
error:can't determine definition of operator ""rol"" -- found 0 possible definitions
 

I don't know a particular VHDL book, although there are surely a lot. Personally, I use the Synopsis manual for reference
,
sometimes even the IEEE specification, although it isn't convenient literature, but some useful constructs aren't mentioned in other literature.

Regarding shift operators, they are defined in packages, the syntax and availability depends on which are imported. Personally I prefer generic VHDL expressions instead:
Code: 
test <= count(2 downto 0) & count(3);
If you want to use the packages, a possible way is to browse the package source code usually present in your tools library folder and understand their definition. Also synopsys manual part 2 deals with standard packages.
 

    A

    aris12

    Points: 2
    Helpful Answer Positive Rating
thanks once again. i did it with your way.
and the manuals looks detailed.
thnx
 

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