Verilog problem with inferred latches for endk

Verilog problem

I am writing a verilog program and some problems were encountered. I just write another small program to try and the same error happens. I would like to know why.

Here's my program.

module abc(input clk, input start, input middle, output [3:0] endkj);

reg [1:0] state, nextstate;
reg [3:0] endk;

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

always @(state or start or middle)
begin
case(state)
S0: begin
if (start == 0)
endk = endk + 1;
else
endk = endk - 1;
nextstate <= S1;
end
S1: begin
if (middle)
endk = endk + 3;
else
endk = endk;
if (endk > 2)
nextstate <= S0;
else
nextstate <= S2;
end
S2: begin
nextstate <= S0;
end
endcase
end

always @(posedge clk)
begin
state <= nextstate;
end
endmodule


In the compilation of the program, it said there are inferred latches for endk. I would like to know why and how to solve this problem.

Thanks.
John

Re: Verilog problem

Inferring latches must not necessarily a problem, but in this case, the arithmetic expressions with endk most likely don't cause the intended behaviour.

You can assign output and internal signals in the asynchronouos always block, but you can't exepect a correct result when counting up or down here. Actually, I don't understand what's exactly intended as condition for counting endk. Do you know it? Anyway the count action should be performed under a @(posedge clk) condition to infer a synchronouos counter.