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Problem with rise and fall times

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master_picengineer

master_picengineer

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Hi all,
I have a Problem when connecting two digital components designed at the transistor level.
The firt module is supposed to controle the second module. When Used alone the rise/fall time of the output signals of the first module are perfect however when the 2 components are connected (output of module 1 to input of module 2) the rise time became huge. I used buffers constructed with 2 inverter but the problem persisted. Please help me solving this problem.

Thanks in advance.
 

Maybe second module's input empendance is low.

apply the output of first modul to a buffer, and connect output of buffer to second modul.

try it, and please write result :)

good luck
 
Thanks my friend for your prompt reply,
I used a buffer as you told me. The buffer is constructed using 2 inverter. The problem still there.
 

maybe you can use emetor output simple amplifier
(gain=1).

86_1204219089.jpg
 

Perhaps you can show us how the second stage is connected to the first stage, how many transistors from the second stage are connected to the first stage etc., also what are transistor sizes you use for the buffer, is the rise time or the fall time that gives you problem?


You can try to increase the n-transistor size of the first inverter and increase the p-transistor size of the second inverter.[/b]
 

connect buffer allone at the o/p of first module resize input side of the buffer to meet the rise and fall time and then try to integrate both modules with optimum sizes.
 

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