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Clock violation, Tetramax

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snr_vlsi

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set split capture_cycle fastscan

Hi,

Can anyone provide me with a solution for avoiding clock not able to capture while other clocks are off (C4) violation while attempting to get test coverage with tetramax for a scan inserted netlist.

I have even tried autofixing the clocks while doing scan insertion, but it is not working.

thx

snr
 

hi,


First thing you need to check is that it is a valid capture clock. If not then remove this clock from the clocks defnition.

If it is a valid clock then you will have to use th GSV of Tetramax to find why is it blocked. Set the pin data to constraint value and trace around the clock to see if it is getting blocked beacause of some other constant pin.

If nothing works.... "set rule C4 ignore" ;-)

vlsi_eda_guy..
 

hi,

Actually the clock which is giving the C4 violation is the reset of the design.

Can the reset definition declared as part of the dft configuration be removed. Is it okay to do this.

By setting C4 as warning, won't the coverage be affected.

thx

S.Nikhil
 

If you are very sure that the reset cannot capture value wih other clocks off , then a safe thing can be to declare the reset as a constant pin with its active-state as the value in which the flop are reset.

Once you do this, this pin will not be seen as clock in Tetramax and you dont get the C4 violation

Yes down grading will hit your test coverage. But if there is no way round, then you will have to downgrade the same.
 

snr_vlsi said:
Hi,

Can anyone provide me with a solution for avoiding clock not able to capture while other clocks are off (C4) violation while attempting to get test coverage with tetramax for a scan inserted netlist.

I have even tried autofixing the clocks while doing scan insertion, but it is not working.

thx

snr
Click to expand...

you can use the switch set split capture_cycle on but its in fastscan mentor graphics

accutally due to C4 violation there will be simulation mismatches
 

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