Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

analog comparator design and phase margin

Status
Not open for further replies.

andy2000a

Advanced Member level 2
Joined
Jul 18, 2001
Messages
597
Helped
14
Reputation
28
Reaction score
8
Trophy points
1,298
Activity points
5,298
comparator design

we usually design OPA and need simulation gain_margin , phase margin ..
for make sure our OPA can really work ..

how about 2 stage comparator ?
in gernel , we design a cmos comparator remove "compenstation cap + resistor"and reduce OP amp layout area , but when we remove compensation
device .. how to simulation garin/phase margin ??

or only simulation offset / PSRR .. open_loop gain

by the way , some comparator like foldcascode .. because comparator work output only Hi & low .. and let gain will small .. how to overcome this problem ?
 

phase margin comparator

OPA usually work with negative feedback, so stability issue is in attention. So we need to simulate gain and phase margins.
Comparators work without negative feedback so frecuency compensation isn't requered. The magnitude of gain and phase margins aren't a matter for comparators. But the position of the first and the second poles are related with the propagation delay of comparator when amplitude of input signal close to resolution. With high input amplitude the propagation delay depend on slewrate behavioural of high inpedance node.
The key parameters of comparator is: gain (resolution), offset, PSRR, CMRR, propagation delay for small and high amplitudes of input step, propagation delay when high input step chages to small input step (restoring).
All above is true for continious time comparators. AC parameters of comparator u can simulate in such maner like OPA.
 

comparator phase margin

do you care group delay?
 

analog comparator design

Normal analog comparator need not care PM,
but if for T-H use that comparator must hold, form feedback loop, you must take care to it.
 

how comparators work

I am puzzle on the comparator, I don't know what to simulation.Every time I just simulate the dc threshold and the transient delay time. In the past I connect the comparator to a dc buffer to simulate the ac gain,but I found the output port work in small signal,the gain is so small. And the gain isn't as same as the gain in dc sweep. Because the comparator work at big sinal mode.
 

opa phase margin

u don't need to care about the pM of the comparator, because it work in the open loop
 

how phase comparators work

The comparators work in the open loop in general, needn't care about the pM.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top