andy2000a
Advanced Member level 2
comparator design
we usually design OPA and need simulation gain_margin , phase margin ..
for make sure our OPA can really work ..
how about 2 stage comparator ?
in gernel , we design a cmos comparator remove "compenstation cap + resistor"and reduce OP amp layout area , but when we remove compensation
device .. how to simulation garin/phase margin ??
or only simulation offset / PSRR .. open_loop gain
by the way , some comparator like foldcascode .. because comparator work output only Hi & low .. and let gain will small .. how to overcome this problem ?
we usually design OPA and need simulation gain_margin , phase margin ..
for make sure our OPA can really work ..
how about 2 stage comparator ?
in gernel , we design a cmos comparator remove "compenstation cap + resistor"and reduce OP amp layout area , but when we remove compensation
device .. how to simulation garin/phase margin ??
or only simulation offset / PSRR .. open_loop gain
by the way , some comparator like foldcascode .. because comparator work output only Hi & low .. and let gain will small .. how to overcome this problem ?