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Why do we write Verilog test bench codes?

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bcdeepak

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hi

i am new to verilog , i am going through some books
i know vhdl

i saw the test bench writing in verilog books

why to write a test bench code ,eventhough in some softwares( i am using Xilinx) we can directly give the waveform (graphical interface) without writing the test-bench code????
 

Re: verilog test bench

It down to complexity. OK, you can 'draw' a test bench in xilinx tools, as long as you are verifying an adder, alu or a counter. but think about verifying say for example H264 decoders. you will have 100s of signal to drive, you will need some random values to be given, you will have to send data for mili-seconds, which some signal changing every clock cycle which can be say 100MHz, 10ns. Can you 'draw' these signals using guis? think...
Kr,
Avi
http://www.vlsiip.com
 

Re: verilog test bench

for system design, its very difficult to test with only waveform files,
where us in testbench you can look for code coverage, branch ,statement..etc and timing too many analysis. abt your design
 

Re: verilog test bench

actually writing a test bench is to check the output you age getting from the code that is written by u.
actally if u write a module like "add" and if u simulate the code then u have to give the values while testing
and in the case of the test bench u can force the values and check the out put
like if u are testing to add 1 and 2, then u can force the values to the module "add" that u have written and directly u can check the outpput
 

Re: verilog test bench

The major advantage of writing test bench is code reusability. you just need to edit the code if you find you have given it wrong.giving signal to huge no.of lines can be easily done here...
 

Re: verilog test bench

for complicated project, testbench perform more coverage and flexible!
 

Re: verilog test bench

hi,
to design complex circuitry you need to write test bench.

thanx......
 

Re: verilog test bench

hi
we need testbench for checking ouput with all possible inputs , but it canot be possible in xilinx at the same time.

for very big complexity type of circuits ,test bench must be needed.
so that
for complicated project, testbench perform more coverage and flexible.
 

Re: verilog test bench

for verilog test bench I found following book good
Kluwer Verilog Quickstart--Practical Guide to Simulation Synthesis in Verilog.


any person who is new in verilog can use this book as quickstart.
 

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