simulate PCI interface

pci32tlite

hi.

how to simulate a PCI target interface core?
i was trying to do that: set command reg, set BAR1 reg, the target generates a response, but if i want to read back a register (BAR1) then it reads zero.(config read) if i want to make a memory read (based on BAR1), then it doesnt response, at any addresses.

the ise8.1 project:
http://buenos.cjb.hu/download/Copyof10.part01.rar
http://buenos.cjb.hu/download/Copyof10.part02.rar
Simulete a post ranslate, because i used ngc blackboxes, and its not possible to simulate just a behavioral model.
this is a PCI to whisbone bridge, a Whisbone intcon and a CAN and GPIO controller.

On the target board (not simulation), if i do memory read, the values are 00 always in the image1 which is the internal memory. in the image0 which is the config space-copy, i can read correct values. I use a a whisbone INJTERCON from the altium designer. If I use the intcon from the opencores.org, then it (the windows) freezes during read.

in simulation, i cant even set the and read the config registers (using config read/write)

simulate pci

heloo
do u hav pci code in verilo/vhdl..
can u mail it to me on swappy.best@gmail.com,.
or anything thing which you hav related to pci bridge....
its an my acadamic project.

pci32tlite+opencores

just look for on www.opencores.org
you will find it. the bci_bridge project is finished, however it doesnt work at me. the pci_blue is as they wrote, not finished...
there is a pci32tlite, also doesn work at me...
the only workin g one is a PCI based LED circuit:
http://www.ben.com/minipci/verilog.php
i am trying to make it to be a wishbone bridge.