EEPuppyPuppy
Junior Member level 3
Code:
module asyn_reset(clk,reset,a,c);
input clk;
input reset;
input a;
output c;
wire clk;
wire reset;
wire a;
reg c;
always @ (posedge clk or posedge reset)
if ( reset == 1'b1) begin
c <= 0;
end else begin
c <= a;
end
endmodule
Above is the code from asic world (https://www.asic-world.com/code/tidbits/asyn_reset.v)
I am confused for the 'always @' and 'if' part about 'reset'.
Since 'always @' holds the condition when we check the if loop. One of the condition is at the rising edge of reset.
If only consider reset, when it is at its rising edge, reset might hold the value from 0 to 1 inclusive. Thus, reset might be some value in between 0 and 1, such as 0.3, when reset hasn't reached 1 yet if it rises slowly.
In this case, reset == 1 condition would fail and reset would fail.
Could anyone please explain this to me?
Thank you so much!