imbichie
Full Member level 6
Hi All,
I am using Xilinx's Vivado 2013.3 for generating the *.bin file.
There are a lot asynchronous paths in my design.
for example if I have grouped the signals like :
# in CLK1 domain
set GROUP1 [get_cells {sig_a1}];
set GROUP1 [get_cells {sig_a2}];
set GROUP1 [get_cells {sig_a3}];
# in CLK2 domain
set GROUP2 [get_cells {sig_b1}];
set GROUP2 [get_cells {sig_b2}];
set GROUP2 [get_cells {sig_b3}];
here the sig_a1 in CLK1 domain driven to sig_b1 in CLK2 domain. Similarly sig_a2 to sig_b2 and sig_a3 to sig_b3.
How we can give the false path here in *.xdc file.
Whether we need to use set_clock_groups or set_false_path in this situation ?
I am using Xilinx's Vivado 2013.3 for generating the *.bin file.
There are a lot asynchronous paths in my design.
for example if I have grouped the signals like :
# in CLK1 domain
set GROUP1 [get_cells {sig_a1}];
set GROUP1 [get_cells {sig_a2}];
set GROUP1 [get_cells {sig_a3}];
# in CLK2 domain
set GROUP2 [get_cells {sig_b1}];
set GROUP2 [get_cells {sig_b2}];
set GROUP2 [get_cells {sig_b3}];
here the sig_a1 in CLK1 domain driven to sig_b1 in CLK2 domain. Similarly sig_a2 to sig_b2 and sig_a3 to sig_b3.
How we can give the false path here in *.xdc file.
Whether we need to use set_clock_groups or set_false_path in this situation ?
