shaiko
Advanced Member level 5
Hello All,
I have a simple question regarding the following VHDL codes:
-- first code
when state_0 =>
if input = '1' then
output <= '0';
end if;
----------------------
-- second code
when state_0 =>
output <= '0';
if input = '1' then
next state <= state_1;
end if;
when state_1 =>
output <= '1';
---------------------
from what I understand, the first code represents a MEALY FSM while the second is MOORE.
Is this correct?
I have a simple question regarding the following VHDL codes:
-- first code
when state_0 =>
if input = '1' then
output <= '0';
end if;
----------------------
-- second code
when state_0 =>
output <= '0';
if input = '1' then
next state <= state_1;
end if;
when state_1 =>
output <= '1';
---------------------
from what I understand, the first code represents a MEALY FSM while the second is MOORE.
Is this correct?